| Commit message (Collapse) | Author | Age | Files | Lines |
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Enable Acoustic noise mitigation for boten and set slew rate to 1/8
which is calibrated value for the board.
BUG=b:180668001
BRANCH=dedede
TEST=build firmware to UPD and Acoustic noise test
Change-Id: I75851bd7c279feeab4ab94f4c82d55bf0e5ce316
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Rename the Kconfig parameter to more accurately reflect what it does.
TPM can be initialised in a different stage too, for instance with
VBOOT it is done in verstage.
Change-Id: Ic0126b356e8430c04c7c9fd46d4e20022a648738
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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Some tests have to be able to catch assertion errors.
Adding CMocka mock_assert() enables that.
Additionally fix test_imd_create_tiered_empty(),
test_full_stack() and test_incorrectly_initialized_stack()
by adding missing expect_assert_failure().
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I5e8dd1b198ee6fab61e2be3f92baf1178f79bf18
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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This guards code accessing the vboot context which does not exist if
vboot starts after romstage.
Change-Id: I2a38daa00d6d18df9c5e22858530814e23bb3e00
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52157
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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Use VPD variable "fsp_dimm_freq" to select DDR frequency limit.
Tested=On OCP Delta Lake, DDR frequency limit can be changed via VPD.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I1232feae5090420d8fa42596b46f2d4dcaf9d635
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
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The intel/soc/broadwell smihandler has no handler for this APM call.
Change-Id: I2bcec7cce00d433a197a9e2fb01434a2998e1452
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52167
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Configure unused GPIOs as NC
BUG=b:180830117
TEST=Build and boot lindar to OS.
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I0ba51dc262ccbf22b45d3be4b65e006f92587fd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Some eMMCs need 80+ms for CMD1 to complete. And the payload may need to
access eMMC in the very early stage (for example, Depthcharge needs it
20ms after started) so we have to start initialization in coreboot.
On Hayato Chromebook this can save ~100ms in total.
BUG=b:177389446
TEST=emerge-asurada coreboot
BRANCH=asurada
Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
Change-Id: I2f58d203e969dc1a13a479d7dc63b1b162a9ae3f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51973
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Select mmc storage config for asurada.
Build MTK host mmc driver.
BUG=b:177389446
TEST=emerge-asurada coreboot
BRANCH=asurada
Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
Change-Id: Iac656d57c2b834d1ce393fd991275b897e597b4b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Add MTK host mmc driver support.
MTK host controller supports eMMC5.1 spec.
BUG=b:177389446
TEST=emerge-asurada coreboot
BRANCH=asurada
Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
Change-Id: I54a7749ed167c00cd631a76af7c67c654c7bc725
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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The conversion to ASL 2.0 syntax in commit 81d55cf introduced a
regression triggering a BUG in Linux when reading the battery current.
Correct the wrongly-converted calculation.
Fixes: 81d55cf ("src/ec/lenovo/h8/acpi/battery.asl: Convert to ASL 2.0")
Tested-by: Andrew A. I. <aidron@yandex.ru>
Change-Id: I1cea8f56eb0a674005582c87cad89f10a02d0701
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52144
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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selecting SOC_AMD_COMMON_BLOCK_USE_ESPI will disable the lpc decodes,
so not selecting that keeps the lpc decodes.
Change-Id: I03a8d4b804cee205b9e06b00e2e5a442452f8f86
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52016
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These changes involve NVMe specific GPIO programming to enable pcie
NVMe SSD boot. Add nvme dev,func in devicetree and also remove
unused GPIOs programmed in Bilby.
Change-Id: I4407f82122c04b13684d4176ba5cd5a9fe03f0db
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51674
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This override was added to have the SCI mapping configured if GPIO was
used as WAKE_L pin. This however didn't set up the SCI level and trigger
information, so it likely never worked as intended.
Change-Id: I44661f05c8f517ece88714c625603579731d174b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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When GPIO_2 was configured as PAD_NF with the WAKE_L function selected
the GPIO_2 override in soc_gpio_hook called soc_route_sci that wrote the
corresponding SCI mapping register, but didn't set up the SCI level and
trigger type, so that couldn't have worked on most of the boards. The
only boards where I think this was actually tested are the google/zork
ones and they configured GPIO_2 as PAD_SCI where the GPIO mux setting is
GPIO mode instead of the WAKE_L mode, but at least the SCI was
configured correctly. The new PAD_NF_SCI macro can configure both the
right GPIO mux setting and set up the SCI configuration correctly, so
use this new macro for the GPIO_2 pin. For test purposes I also added
the corresponding GPIO_2 configuration to amd/mandolin to see if the
affected registers end up having the expected value using the HDT
debugger to look at the registers, but didn't test the wake-up
functionality, since S3 resume isn't working on amd/mandolin yet.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Change-Id: Ic069e46b759fb6746645faccd254263c49a892d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51756
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The CACHE_MRC_SETTINGS option is already selected in SoC Kconfig.
BUG = N/A
TEST = Build and boot facebook FBG1701
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Change-Id: I1c7fd5ec36726724939660bf506a45a44848f8c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52152
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Update the ACPI name from AMDP1015 to 1002105 based on b/177971830#180.
AMDI1015 -> AMD platform with RT1015
10021015 -> AMD platform with RT1015p
Reference:
https://www.spinics.net/lists/alsa-devel/msg124694.html
BUG=b:177971830
BRANCH=firmware-zork-13434.B
TEST=emerge-zork coreboot chromeos-bootimage, then verify with ALC1015 AMP
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: Id8f378ad6f3328d7db949ecdb609a2f16acd3884
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52127
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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We seperate the EoTp packet extra data. So need to reduce the delta.
BUG=b:173603645
BRANCH=kukui
TEST=Display is normal on Kukui
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Change-Id: I0666068cfb04b78eb706278814163f050da32b9c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51432
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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This change hooks up the new gpio operations in DNV-NS.
Change-Id: I2179e641153da7230467c5766e4ded58fdb90292
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48618
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This commit includes makefile cleanup to exclude common source file
compilation in each stage by using all-y flag.
BUG=b:182963902
TEST=trogdor validated on limozeen
Change-Id: I48464567974a0729c1c6b6157bcce4fac39a8b38
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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PS/2 keyboard used IRQ 1.
BUG=none
TEST=Boot guybrush and see internal keyboard working
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I97b7382eac28aae2cc82f430c58cf8066b9701e1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52143
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Guybrush doesn't have a PS/2 mouse.
BUG=none
TEST=boot guybrush to the OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I87e51d23b69cfd6ad7bb88b364714d679e92728f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52145
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This register is used for masking/unmasking eSPI IRQs.
BUG=none
TEST=Build guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia209539b2e0ce390e227757b16c2969b9124a845
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52142
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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To train PCIe devices, the devices need to be enabled and taken out of
reset. This patch does the bare minimum needed to train PCIe. It is
not intended to handle timings, which will be addressed later.
Copy the enables for WWAN & WLAN into early GPIO Init so that they're
enabled before FSP-M runs and trains the PCIe busses.
Again, this patch is the minimum to let the FSP train the PCIe busses.
BUG=b:182202136
TEST=Boot guybrush from NVME.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I3807e02de1e9ae40b0a4162217afd6aabb5b04ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52115
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This option's value is not used anywhere. Remove it.
Change-Id: I0f30cddd30d459f48b51f377b111bbc04709c5f8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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It is zero for all mainboards. If one really wanted to ignore VT-d
support, a user-visible Kconfig option would be a better approach.
Change-Id: I320c10317f3fabee5443c16ebdf1ffd0e24193b8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Commit 0591348833f730a42e74039d8e2d957ec94a39d5 introduced this Kconfig
option inside soc/intel/common scope. However, it was only hooked up in
commit d74cd60b8159c3928dba318e6387f200ff3bb0e7 for Alder Lake, and in
commit 99157c1f4a80556462ca22a4ade87b2c8d09e674 for Tiger Lake. Hook up
the `SOC_INTEL_DISABLE_IGD` Kconfig option to all other platforms which
have the `InternalGfx` UPD.
Change-Id: Icd1379a835b445a6d4b028ebde5a3e355ee5b67b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52100
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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WFC Camera driver will control the power sequence.
Therefore, set default to low.
BUG=b:184024459
TEST=abuilds
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I7ce25b83a715a022e36289dc0abf0d39f5798eb0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Update devicetree and gpio setting of metaknight to handle pen detection.
BUG=b:180426949
TEST=Build and check behavior is expected.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ieeca20eff57b16217a13d996dca3f662911f3e5a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I50e88ac946b9d8797571f9e3d4b325db760e423f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51932
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This is a temporary workaround for a bug that breaks graphics due to
some power management issue.
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie4c8ff8e827901112fd8b2e993898006bc133241
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52141
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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pcie_rst isn't working correctly, so use the AUX resets to reset the
PCIe devices before training.
BUG=b:182202136
TEST=See PCIe devices train & enumerate
Change-Id: I6db21c79dcbd40c7a8c3f01c60b02882a3851278
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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TEST=Worked on Matt's Majolica board.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Change-Id: I65c7e0ebf1e43fd4608d46bae8a176cfc3d0236b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51956
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I838aeda2e6c403eaa3388a6b934e7ab6b4e918e3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Change-Id: Ic8a4349315f8759c79dc6b087b2a933c307cd573
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51957
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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This patch adds the functionality to write the DXIO and DDI descriptors
to the UPD data structure to the SoC code and adds the
mainboard_get_dxio_ddi_descriptors function to each mainboard using the
Cezanne SoC that gets called to get the descriptors from the board code.
Change-Id: I1cb36addcf0202cd56ce99e610a13d6d230bc981
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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This allows coreboot to easily iterate over the descriptors.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2ecb3b543f90b8c6a957794f0c55b0ba5c72d59d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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The UPD header files get generated as part of the FSP build process. For
the initial Cezanne development we took the Picasso UPD data structures
as a starting point. This patch replaces it with the first version of
the Cezanne-specific UPD data structures that is present in version 12
of the internal work-in-progress FSP binary drops.
The serial_port_stride UPD-M field is removed, since the information is
already given by serial_port_use_mmio. The stride is 4 bytes for the
MMIO UART case and 1 byte for the legacy I/O case.
BUG=b:182524631
TEST=NVMe works on google/guybrush when the rest of the patch train is
applied as well.
Change-Id: Idca235029bf2e68d403230d55308820cab61a6c0
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib16f133b270c99c6e060e5bd0c156cbb03293474
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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BUG=b:182211161
TEST=builds
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I375ad38da14189de2ae2713082a80e8cdb2fe5f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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BUG=b:182211161
TEST=builds
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Id6c20b32ddafe415132ce70abf5381ff3aad13f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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BUG=b:182211161
TEST=builds
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I850a3ecc8776593d97f4162e812a39991caa30ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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GPIOs should be configured in ramstage even if they are configured in an
earlier stage.
BUG=b:182211161
TEST=builds
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I07d5c46d6ea6dc2bc9ab265d0c01772d653884cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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BUG=b:182211161
TEST=builds
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I2d4ec1556ac7136c454eb025ff99aafbf49b8982
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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BUG=b:182211161
TEST=builds
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I1d28c2335b095a77285dcb261a0dffe96d129c46
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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BUG=b:182211161
TEST=builds
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I9768feaadf2423acd50a71e9a2310b4ab2d1a2a8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Following commit de50d39, remove the `volume` entry from cmos.default.
Change-Id: Ieebafffa0d2fbf6cdd24cff4ddefe090a727cbfa
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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On VCCin there was an oscillation which occurred just as the kernel
started (kernel starting... message). On some devices, this behavior
seems even worse. In previous platforms VCCin toggled for a few ms
and then was stable. For volteer, this happens at the same point in
time for around 40ms. However, it starts oscillating again later in
the boot sequence. Once at the root shell, it seems to oscillate
indefinitely at around 100-200Hz (very variable though). To fix this
we need to control the deep C-state voltage slew rate.We have options
for controlling the deep C-state voltage slew rate through FSP UPDs.
This patch expose the following FSP UPD interface into coreboot:
- AcousticNoiseMitigation
- FastPkgCRampDisable
- SlowSlewRate
We are setting SlowSlewRate for all volteer boards to 2 which is Fast/8.
TGL has a single VR domain(Vccin). Hence, the chip config is updated to
allow mainboards to set a single value instead of an array and FSP UPDs
are accordingly set.
BUG=b:153015585
BRANCH=firmware-volteer-13672.B
TEST= Measure the change in noise level by changing the UPD values.
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Change-Id: Ica7f1f29995df33bdebb1fd55169cdb36f329ff8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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From Skylake/Sunrise Point onwards, there are two BIOS_CNTL registers:
one on the LPC/eSPI PCI device, and another on the SPI PCI device. When
the WPD bit changes from 0 to 1 and the LE bit is set, the PCH raises a
TCO SMI with the BIOSWR_STS bit set. However, the BIOSWR_STS bit is not
set when the TCO SMI comes from the SPI or eSPI controller instead, but
a status bit in the BIOS_CNTL register gets set. If the SMI cause is not
handled, another SMI will happen immediately after returning from the
SMI handler, which results in a deadlock.
Prevent deadlocks by clearing the SPI synchronous SMI status bit in the
SMI handler. When SPI raises a synchronous SMI, the TCO_STS bit in the
SMI_STS register is continously set until the SPI synchronous SMI status
bit is cleared. To not risk missing any other TCO SMIs, do not clear the
TCO_STS bit again in the same SMI handler invocation. If the TCO_STS bit
remains set when returning from SMM, another SMI immediately happens and
clears the TCO_STS bit, handling any pending events.
SPI can also generate asynchronous SMIs when the WPD bit is cleared and
one attempts to write to flash using SPI hardware sequencing. This patch
does not account for SPI asynchronous SMIs, because they are disabled by
default and cannot be enabled once the BIOS Interface Lock-Down bit in
the BIOS_CNTL register has been set, which coreboot already does. These
asynchronous SMIs set the SPI_STS bit of the SMI_STS register. Clearing
the SPI asynchronous SMI source should be done inside the SPI_STS SMI
handler, which is currently not implemented. All of this goes out of the
scope of this patch, and is currently not necessary anyway.
This patch does not handle eSPI because I cannot test it, and knowing if
a board uses LPC or eSPI from common code is currently not possible, and
this is beyond the scope of what this commit tries to achieve (fix SPI).
Tested on HP 280 G2, no longer deadlocks when SMM BIOS write protection
is on. Write protection will be enforced in a follow-up.
Change-Id: Iec498674ae70f6590c33a6bf4967876268f2b0c8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50754
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit 52e61945588bc327844acc4658426861d63ad189.
Reason for revert: Graphics actually works now. I should have abandoned this CL.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I83aac3a2c616bb434706f23e36549760bc764080
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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