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* soc/intel/common: Include Alder Lake device IDsSubrata Banik2020-08-0519-2/+447
| | | | | | | | | | | | | | | Add Alder Lake specific CPU, System Agent, PCH (Alder Point aka ADP), IGD device IDs. Document Number: 619501, 619362 Change-Id: I17ce56a220e4dce2db2e0e69561b3d6dac9e65a2 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* nb/intel/x4x: Define and use `HOST_BRIDGE` macroAngel Pons2020-08-046-52/+52
| | | | | | | | | | | | Other Intel northbridges do this. Tested with BUILD_TIMELESS=1, Asus P5QL PRO does not change Change-Id: I50785b7bf3e3cc0eade7fda4b4b2e2bb71a54c31 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* Revert "device/pci_device.c: Do not complain about disabled devices"Nico Huber2020-08-041-4/+0
| | | | | | | | | | | | | This reverts commit ad247ac5d8ef4a38bd1d61fbd28076f343a46c5c. It doesn't work like this. The `dev->enable` field has already been updated and is always `0` at this point. Change-Id: I5b3560dcea2f226c841f4823526db2fdab149d22 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/intel/skylake: Add RMRRs after all DRHDsAngel Pons2020-08-041-11/+18
| | | | | | | | | | | | | | | | The VT-d architecture specification (Doc. D51397-011, Rev. 3.1) says: BIOS implementations must report these remapping structure types in numerical order. i.e., All remapping structures of type 0 (DRHD) enumerated before remapping structures of type 1 (RMRR), and so forth. So, update the corresponding code to adhere to the specification. Change-Id: I2446d536603559f637f3f8b1b44e9d712aa35492 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
* soc/intel/broadwell: Add RMRRs after all DRHDsAngel Pons2020-08-041-11/+18
| | | | | | | | | | | | | | | | The VT-d architecture specification (Doc. D51397-011, Rev. 3.1) says: BIOS implementations must report these remapping structure types in numerical order. i.e., All remapping structures of type 0 (DRHD) enumerated before remapping structures of type 1 (RMRR), and so forth. So, update the corresponding code to adhere to the specification. Change-Id: Ib5ef5e006e590d72bec52e057e9b72150e0e636f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
* soc/intel/apollolake/acpi.c: Add RMRRs after all DRHDsAngel Pons2020-08-041-8/+13
| | | | | | | | | | | | | | | | The VT-d architecture specification (Doc. D51397-011, Rev. 3.1) says: BIOS implementations must report these remapping structure types in numerical order. i.e., All remapping structures of type 0 (DRHD) enumerated before remapping structures of type 1 (RMRR), and so forth. So, update the corresponding code to adhere to the specification. Change-Id: I4ee3ae6c45e2a2c921fbccbb62b853e4a141a58d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44110 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
* nb/intel/sandybridge/acpi.c: Add RMRRs after all DRHDsAngel Pons2020-08-041-16/+22
| | | | | | | | | | | | | | | | The VT-d architecture specification (Doc. D51397-011, Rev. 3.1) says: BIOS implementations must report these remapping structure types in numerical order. i.e., All remapping structures of type 0 (DRHD) enumerated before remapping structures of type 1 (RMRR), and so forth. So, update the corresponding code to adhere to the specification. Change-Id: I1f84cae41c6281e0d545669f1e7de5cab0d9f9c0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44109 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
* nb/intel/x4x: Remove dead assignmentsAngel Pons2020-08-041-2/+1
| | | | | | | | | | The call to `decode_pcie_bar` always initializes these values. Change-Id: Iffdb2fc846a6fc1a1abc504370b6283e292b61c0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* soc/amd/picasso/acpi: clean up global NVSFelix Held2020-08-042-40/+20
| | | | | | | | | | | | | | | | Some fields in GNVS seem to be copied over from Apollolake to Stoneyridge to Picasso. This patch removes the unused fields. BUG=b:161165393 TEST=Mandolin still boots and dmesg shows no new ACPI errors. Change-Id: I8c6b580543089bf0180a7caeb9e6a47dc4ed4a1d Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* nb/intel/x4x: Refactor `decode_pcie_bar`Angel Pons2020-08-041-9/+5
| | | | | | | | | | | | Constify and eliminate local variables where possible to ease reading. Tested with BUILD_TIMELESS=1, Asus P5QL PRO does not change. Change-Id: I6d2937146a4764823cfc45c69a09f734b2525860 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* nb/intel/ironlake/acpi.c: Factor out PCIEXBAR decodingAngel Pons2020-08-041-28/+28
| | | | | | | | | | | Other northbridges have a `decode_pcie_bar` function. Since it's not needed anywhere else, keep it as a static function for now. Change-Id: Ide42ffcebb73c3e683e0ccaf0ab3aeae805d1123 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* nb/intel/i945: Deduplicate PCIEXBAR decodingAngel Pons2020-08-043-32/+7
| | | | | | | | | | We can use `decode_pcie_bar` instead, if we make it non-static. Change-Id: Ic39f3df0293b4d44f031515b1f868e0bb9f750c9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44145 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* nb/intel/i945: Refactor `get_pcie_bar`Angel Pons2020-08-041-19/+20
| | | | | | | | | | Turn it into `decode_pcie_bar`, taken from gm45. Change-Id: I81a398535f18ced10b5521bddcf21f3568e1d854 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* nb/intel/haswell: Use ASL 2.0 syntaxAngel Pons2020-08-041-3/+3
| | | | | | | | | | | Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change. Change-Id: I9c69028ff13efa6999b6110fbcd9233a09def991 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44152 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
* sb/intel/i82801gx: Use PCI bitwise opsAngel Pons2020-08-048-127/+45
| | | | | | | | | | | | While we are at it, also reflow a few lines that fit in 96 characters. Tested with BUILD_TIMELESS=1, Getac P470 does not change. Change-Id: I2cc3e71723e9b6898e6ec29f0f38b1b3b7446f09 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* nb/intel/ironlake/acpi/hostbridge.asl: Use ASL 2.0 syntaxAngel Pons2020-08-041-34/+32
| | | | | | | | | | | | | This brings Ironlake closer to Sandy Bridge. Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change. Change-Id: Idde75e7295f642f8add34168bffe5851ea02fbc6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43687 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/intel/sandybridge: Update to ASL 2.0 syntaxAngel Pons2020-08-041-4/+4
| | | | | | | | | | | Tested with BUILD_TIMELESS=1, Lenovo ThinkPad X230 remains identical. Change-Id: Ie3570cd0a75c6b34581b35165c1c6393214ad0bb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
* nb/intel/x4x: Change signature of `decode_pciebar`Angel Pons2020-08-044-4/+4
| | | | | | | | | | Rename it and make it return an int, like other northbridges do. Change-Id: I8bbf28350976547c83e039731d316e0911197d54 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* nb/intel/haswell: Deduplicate PCIEXBAR decodingAngel Pons2020-08-043-35/+11
| | | | | | | | | | Add `decode_pcie_bar` for consistency with other Intel northbridges. Change-Id: If04ca3467bb067b28605a3acccb8bda325735999 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* nb/intel/pineview: Refactor `decode_pcie_bar`Angel Pons2020-08-041-9/+5
| | | | | | | | | | | | Constify and eliminate local variables where possible to ease reading. Tested with BUILD_TIMELESS, Foxconn D41S remains identical. Change-Id: Iaad759886a8f5ac07aabdea8ab1c6d1aa7020dfc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44140 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* nb/intel/pineview: Change signature of `decode_pciebar`Angel Pons2020-08-044-4/+4
| | | | | | | | | | Rename it and make it return an int, like other northbridges do. Change-Id: Id526ff893320a77e96767ec642c196c2196f84e1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44139 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* nb/intel/pineview: Use `MiB` definitionAngel Pons2020-08-043-9/+10
| | | | | | | | | | | | Also constify a local variable while we're at it. Tested with BUILD_TIMELESS=1, Foxconn D41S does not change. Change-Id: I90ab35932d7c0ba99ca16732b9616f3a15d972dd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mb/google/zork/var/vilboz: Enable support for garaged stylusFurquan Shaikh2020-08-041-0/+12
| | | | | | | | | | | | | This change adds support for pen insert/eject operations in S0 and wake on pen eject from S3 for vilboz. BUG=b:157628650 Change-Id: I7ba0881b67dfb67c032667d591f7d1806a50af22 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* mb/kontron/bsl6: Add new Skylake COMe moduleNico Huber2020-08-0421-0/+794
| | | | | | | | | | | | | | | | Add Kontron/bSL6 together with Siemens/Boxer26, a baseboard for the bSL6. The plain bSL6 variant received little testing and only during early development. The Boxer26 variant is actively used and fully tested. The latest rebase was boot tested with FILO and Linux 4.19. Change-Id: If2b6a3f1e9dd095463f1f1521068b9f66a9189c5 Signed-off-by: Nico Huber <nico.huber@secunet.com> Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29480 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/baytrail: Factor out `acpi_fill_madt()`Angel Pons2020-08-043-35/+15
| | | | | | | | | | | It is the same for the two Bay Trail boards in the tree. Change-Id: I5110cfa8807406232e4f7f1fe79dfe9c3ae4dac4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Máté Kukri <kukri.mate@gmail.com>
* mb/supermicro/x11ssh-tf: Drop `PcieRpClkReqSupport` linesAngel Pons2020-08-041-4/+0
| | | | | | | | | | | | They default to zero already, so we might as well drop them. Tested with BUILD_TIMELESS=1, its coreboot.rom does not change. Change-Id: I3c04240b270f51d584f879e1344301679f133fdb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43928 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/intel/pineview: Remove dead assignmentsAngel Pons2020-08-041-2/+1
| | | | | | | | | | The call to `decode_pciebar` always initializes these values. Change-Id: Ide45e1e5e8b8d6cfebd2fc4e272b1971b0a9b346 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* nb/intel/gm45: Deduplicate PCIEXBAR decodingAngel Pons2020-08-043-32/+6
| | | | | | | | | | We can use `decode_pcie_bar` instead, if we make it non-static. Change-Id: I4d005290355e30e6fdaae3e8e092891fddfbe4fc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* nb/intel/gm45/northbridge.c: Use `MiB` definitionAngel Pons2020-08-041-3/+4
| | | | | | | | | | Tested with BUILD_TIMELESS=1, Roda RK9 does not change. Change-Id: Ibfa9a6fa7818d0bd79d2c0d9331c0ca38a2b7fe3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
* nb/intel/gm45: Use PCI bitwise opsAngel Pons2020-08-048-140/+74
| | | | | | | | | | | | | | While we are at it, also reflow a few lines that fit in 96 characters. Tested with BUILD_TIMELESS=1, Roda RK9 does not change. Change-Id: Icaca44280acdba099a5e13c5fd91d82c3e002bae Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42189 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/**/{devicetree,overridetree}.cb: Indent with tabsAngel Pons2020-08-0422-210/+210
| | | | | | | | | | | | Use tabs instead of eight (sometimes less) spaces. Change-Id: Ic3d61f5210d21d9613fc50b47b90af71f544169a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* nb/intel/i440bx: Make ROM area unavailable for MMIOKeith Hui2020-08-041-0/+1
| | | | | | | | Change-Id: Iede1452cce8a15f85d70a3c38b4ec9e2d4a54f9e Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* src/lib: Remove unused function parameters in imd.cAnna Karas2020-08-044-15/+14
| | | | | | | | | | | | | Remove const struct imd *imd and const struct imdr *imdr parameters from the prototypes of imdr_entry_size(), imd_entry_size() and imd_entry_id() functions since they are not used anywhere. Signed-off-by: Anna Karas <aka@semihalf.com> Change-Id: I6b43e9a5ae1f1d108024b4060a04c57f5d77fb55 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43999 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/gizmosphere/gizmo/mainboard.c: Remove white space after 'mdelay'Elyes HAOUAS2020-08-031-1/+1
| | | | | | | | Change-Id: Ib7c6ab0a2e5a03f30b70c4bbb1091fa9c689c23b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44094 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/zork: Pass oscout system clk to rt5682Akshu Agrawal2020-08-032-2/+8
| | | | | | | | | | | | | | | | | | In kernel clk for AMD SoCs we expose a generic clk by the name oscclk1. This oscclk1 is a fixed 48Mhz frequency clk in RV. In Zork oscout system clock is linked to rt5682 mclk. Setting mclk-name to oscclk1 tells rt5682 driver its mclk is oscclk1. Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> BUG=b:158906189 TEST=rt5682 driver get the correct clk and tested audio playback Change-Id: Ic565e8e0573e085e5759b2d3688cc0a4533b67fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/44010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* soc/amd/picasso: set is_rv to 1 for RV familyAkshu Agrawal2020-08-031-0/+8
| | | | | | | | | | | | | | | | RV has difference in clk framework. In RV we get a 48Mhz fixed clk, while in ST we had 25Mhz, 48mhz clocks and a Mux to select between them. To differentiate set the fmw property to 1 for boards using RV family of SoC. Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> BUG=b:158906189 TEST=rt5682 driver get the correct clk and tested audio playback Change-Id: I685ded1607c2c7edc5e48f0bada258ebde192bb8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* mb/bostentech: Add GBYT4 portMate Kukri2020-08-0319-0/+674
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Single channel DDR3L: requires mrc.bin (extracted from ChromeBook firmware) - Tested, working with: 2GB SK Hynix stick, 4GB Samsung stick - VGA: Video works with VGA rom extracted from UEFI - SeaBIOS (runs the option rom) tested, works in text mode - GRUB2 (coreboot runs the option rom) tested, works in VESA mode, no video in text mode - USB: Both USB2.0 ports work using the EHCI controller - Works in both SeaBIOS, GRUB2 and Linux - Serial: driven by an IT8728F SuperIO - Works as a console in coreboot, SeaBIOS and GRUB2 - Works with interrupts in Linux after a cold boot, after a warm reboot IRQs get lost - SATA: 2 ports on board (one is mSATA) - SATA init works with both refcode.elf and native refcode (patch CB:43133) - Booting from SATA works with GRUB2, SATA works in Linux - Patch CB:44088 fixes SATA in SeaBIOS - 4 PCIe Intel ethernet controllers - Only tested in Linux, all 4 work with the igb driver - Power button, reset button and both indicator LEDs work - Optional fan header is not tested as the appliance is passively cooled - TXE (ME): optional, does not shut down after 30 minutes without the TXE blob - Works with TXE blob left as is, shows up on PCI - Works with the entire TXE section wiped, no device on PCI, intelmetool can't find anything Used rambi as an example, but almost everything is modified as the two boards are very different. Signed-off-by: Mate Kukri <kukri.mate@gmail.com> Change-Id: I99ed0c94c3255578151f940ad9b274e6f0816bfe Reviewed-on: https://review.coreboot.org/c/coreboot/+/43087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/intel/baytrail: Add MRC SMBus workaroundMate Kukri2020-08-031-1/+17
| | | | | | | | | | | | - The Bay Trail MRC fails to read the SPDs from SMBus. - Instead the SPDs are read into a buffer and the buffer is passed to the MRC. Change-Id: I7f560d950cb4e4d118f3ee17e6e19e14cd0cc193 Signed-off-by: Mate Kukri <kukri.mate@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44092 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* lib/gcov: Remove assert(0)Patrick Georgi2020-08-031-1/+1
| | | | | | | | | | | | | | | | This follows CB:44047 which probably missed this because it's a custom assert macro (in code that has only recently been added to build checks). Without this change, building with gcov fails because gcc_assert(0) can be build-time verified (as introduced by CB:44044) while we need runtime failure semantics here. Change-Id: I71a38631955a6a45abe90f2b9ce3a924cc5d6837 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44105 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
* soc/intel/xeon_sp/cpx: configure STACK_SIZEJonathan Zhang2020-08-031-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | Before this change, we have this problem (boot log from DeltaLake config A server): Jumping to boot code at 0x00040000(0x755f6000) Stack overrun on CPU0 (address 0x7574a000 overwritten). Increase stack from current 4096 bytes ERROR: BUG ENCOUNTERED at file 'src/lib/stack.c', line 43 Linux version 4.16.18 Configure STACK_SIZE to make it larger to fix above problem. Now, we have this boot log: BS: BS_PAYLOAD_LOAD exit times (exec / console): 326 / 21727 ms Jumping to boot code at 0x00040000(0x752f2000) CPU0: stack: 0x75746000 - 0x7574a000, lowest used address 0x7574681c, stack used: 14308 bytes Linux version 4.16.18 TESTED=booted YV3 config A to target OS. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Ia04a3ee0cd37177ecab65469855a1cf920742458 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/intel/xeon_sp/cpx: enable PLATFORM_USES_FSP2_2Jonathan Zhang2020-08-035-21/+22
| | | | | | | | | | | | | | | | | | | | | | CPX-SP FSP is FSP 2.2, so select PLATFORM_USES_FSP2_2. SKX-SP continues to select PLATFORM_USES_FSP2_0, as SKX-SP FSP is FSP 2.0. Correct DCACHE_RAM_BASE. Increase FSP_TEMP_RAM_SIZE, DCACHE_BSP_STACK_SIZE, and adjust DCACHE_RAM_SIZE accordingly. Thus the workaround of hardcoding StackBase and StackSize FSP-M UPD parameters is removed. Add CPX-SP soc implementation of soc_fsp_multi_phase_init_is_enable() to indicate that FSP-S multi phase init is not enabled, since it is not supported by CPX-SP FSP. TESTED=booted YV3 config A to target OS. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I25e39083df1ebfe78871561b0a0e230b66524ea9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44049 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/asrock/h110m: Relocate devicetree settingsAngel Pons2020-08-031-114/+97
| | | | | | | | | | | | Some settings are suspicious, and have been annotated with FIXMEs. Tested with BUILD_TIMELESS=1, its coreboot.rom does not change. Change-Id: I7755867cb92745f542a4261db5dd118ca905612b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* nb/intel/ironlake: Add Generic Non-Core register definitionsAngel Pons2020-08-033-4/+8
| | | | | | | | | | Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change. Change-Id: I4d878b5dbb5a5617143240b8f5bc5b6f5a754511 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* nb/intel/ironlake: Add Generic Non-Core PCI device definitionAngel Pons2020-08-033-4/+9
| | | | | | | | | | Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change. Change-Id: I8feff0d71ad70ac994e29b238d35e2c73aa92ecd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43739 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* nb/intel/ironlake: Add QPI Physical Layer registersAngel Pons2020-08-032-13/+23
| | | | | | | | | | Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change. Change-Id: I44db564c757647f493e92d35602178ef8b722517 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* nb/intel/ironlake: Add QPI Physical Layer device definitionAngel Pons2020-08-032-13/+18
| | | | | | | | | | | | | Like the QPI Link device, there can be more of these devices on multi-socket platforms. So, name it Physical Layer 0. Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical. Change-Id: Ia5f6e42a742bc69237de38f1833e56c8da7c4f7e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* nb/intel/ironlake: Add QPI Link register definitionsAngel Pons2020-08-032-5/+10
| | | | | | | | | | Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change. Change-Id: Id226a2fdcbd0fe48822c4f65746e14fb00db6b2e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* nb/intel/ironlake: Add definition for QPI Link PCI deviceAngel Pons2020-08-032-5/+10
| | | | | | | | | | | | | | On multi-socket platforms, there can be two QPI buses, each with its own PCI device. We only have one QPI link on Arrandale, though. In case support for multi-socket processors ever gets added, name it Link 0. Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change. Change-Id: I6481154a2d1cc1c84c1f167a374a62af3b2cf3d8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* nb/intel/ironlake: Add SAD DRAM register definitionsAngel Pons2020-08-032-4/+7
| | | | | | | | | | Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change. Change-Id: I66b87d15f6b741c6fc935106c35b201fbd9ab2c6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* nb/intel/ironlake: Correct PCIEXBAR definitionAngel Pons2020-08-034-4/+5
| | | | | | | | | | This register resides within the SAD's config space, and is 64-bit. Change-Id: I19458f7c6be6b1a5fcd47ac93ee0597f1251a770 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-12 10:17:43 +0000