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* mb/google/fatcat/var/felino: Add ALC1320 codec to devicetreeWeimin Wu2025-04-112-0/+8
| | | | | | | | | | | | | | | | | | Update devicetree to support Realtek ALC1320 codec. The ALC1320 soundwire class_id is MIPI_CLASS_SDCA(1). BUG=b:378629979 TEST=emerge-fatcat coreboot check the ssdt dump PCI0.HDAS.SNDW including 0x000331025D132001 Change-Id: Ie8763888810f56eb45523e3bcf7ef082900b1225 Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86747 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Mac Chiang <mac.chiang@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jayvik Desai <jayvik@google.com> Reviewed-by: Pranava Y N <pranavayn@google.com>
* drivers/soundwire/alc1320: use common struct to set soundwire ADDR_Mac Chiang2025-04-112-10/+8
| | | | | | | | | | | | | | | | | | | | | Add common soundwire address struct for acpi table configuration over overridetree. refer to: commit 2411942a0518 ("drivers/soundwire/alc711: Add common Kconfig for ALC7xx soundwire codecs") BUG=b:378629979 TEST=emerge-fatcat coreboot check the ssdt dump PCI0.HDAS.SNDW has address: 0x000331025D132001 Change-Id: I2d3531eef6adf21a28a26dcc3ac1bb7830877905 Signed-off-by: Mac Chiang <mac.chiang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Pranava Y N <pranavayn@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/fatcat/var/felino: Add ALC712 codec to devicetreeWeimin Wu2025-04-101-3/+42
| | | | | | | | | | | | | | | | | | Update device tree to support Realtek ALC712 codec. reference datasheet: Realtek ALC712-VB-CG Rev. 0.24 BUG=b:378629979 TEST=emerge-fatcat coreboot check the ssdt dump PCI0.HDAS.SNDW has address: 0x000330025d071201 Change-Id: Ic5c38462cd1ab39d4aebc324d5151cb4337051df Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85572 Reviewed-by: Jayvik Desai <jayvik@google.com> Reviewed-by: Pranava Y N <pranavayn@google.com> Reviewed-by: Mac Chiang <mac.chiang@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/soundwire: Support Realtek ALC712 codecWeimin Wu2025-04-103-1/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | Update SoundWire driver to support ALC712 audio codec. reference datasheet: Realtek ALC712-VB-CG Rev. 0.24 BUG=b:378629979 TEST=emerge-fatcat coreboot A sound can be heard from the speaker, the test instructions are as follows: amixer -c 0 cset name='rt712 OT23 L Switch' on amixer -c 0 cset name=''rt712 OT23 R Switch' on amixer -c 0 cset name='rt1320-1 OT23 L Switch' on amixer -c 0 cset name='rt1320-1 OT23 R Switch' on amixer -c 0 cset name='Speaker Switch' on speaker-test -D hw:0,2 -c 2 -t sine -f 440 Change-Id: Ib79896a9fe23f2f66d6ee3a24f5a62bfa0f7a649 Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Mac Chiang <mac.chiang@intel.com>
* device/Kconfig: Make option to allocate above 4G appear in KconfigAlicja Michalska2025-04-091-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously only tested on server platforms - it wasn't working correctly on consumer platforms due to missing boolean. This patch fixes it, which makes resource allocator use uint64 instead of uint32. Thanks to that, modern GPUs like Intel Arc or Radeon RX now work correctly with ReBAR enabled, and correctly initialize the framebuffer in payload (i.e EDK2) after initializing the OpROMs. Example of issue caused by resource allocator using uint32 (Intel Arc A580): [ERROR] Resource didn't fit!!! [ERROR] PCI: 00:01:00.0 10 prefmem64 size: 0x0000800000 not assigned [ERROR] PCI: 00:03:00.0 18 prefmem64 size: 0x0200000000 not assigned (Followed by Linux reporting that BAR space was limited to 256MB, which severely hindered the performance). TESTed on Intel Tiger Lake-H (mb/erying/tgl) with Intel Arc A580 and AMD Radeon RX7800XT. Change-Id: Ia17b3312016409d8fd6bcce4321481a7b7e35ce5 Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mainboard/protectli/vault_ehl/Kconfig: Configure TPM PIRQMichał Żygowski2025-04-091-0/+3
| | | | | | | | | | | | | | | | The board uses GPP_G19 as GPIO interrupt for SPI dTPM. The pad is already configured as APIC interrupt, so simply define the TPM_PIRQ to GPP_G19_IRQ, which is 0x6B for Elkhart Lake. TEST=Boot Ubuntu 24.04 and check dmesg that Linux does not complain on TPM interrupt not working. Check Windows Device Manager does not report any problem with TPM and its resources. Change-Id: Ia23319680cff927f10b44d7a5d07928cc30dbc9d Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87051 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8189: Reserve DRAM buffers for HW TX TRACKINGMike Lin2025-04-092-0/+8
| | | | | | | | | | | | | | | | | | | | | HW TX tracking works by writing a pattern to the designated DRAM buffer and then reading it back automatically to calculate the appropriate TX time delay. To avoid writing the pattern to system-used memory, we need to permanently reserve last 64KB memory on each rank for the HW TX tracking feature. BUG=b:379008996 BRANCH=none TEST=Reserve memory ok Firmware shows the following log : 000000013fff0000-000000013fffffff: RESERVED 000000023fff0000-000000023fffffff: RESERVED Signed-off-by: Mike Lin <mike.lin@mediatek.corp-partner.google.com> Change-Id: I2ecfe42dc9f1882163d03f50cf9b5ff8e98c2972 Reviewed-on: https://review.coreboot.org/c/coreboot/+/87039 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
* mb/google/skywalker: Add DRAM calibration init entryMike Lin2025-04-091-1/+2
| | | | | | | | | | | | | | | | | | Add DRAM calibration entry in romstage. BUG=b:379008996 BRANCH=none TEST=Boot up pass 3200 LPDDR5 chan0(x16) rank0: memory test pass 3200 LPDDR5 chan0(x16) rank1: memory test pass 3200 LPDDR5 chan1(x16) rank0: memory test pass 3200 LPDDR5 chan1(x16) rank1: memory test pass Signed-off-by: Mike Lin <mike.lin@mediatek.corp-partner.google.com> Change-Id: Iabdcabefc77a262c548019e801daf5b269eaa97a Reviewed-on: https://review.coreboot.org/c/coreboot/+/87038 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/skywalker: Set up USB host in ramstageLiu Liu2025-04-091-1/+2
| | | | | | | | | | | | | | Add USB host function support. BUG=b:379008996 BRANCH=none TEST=boot to kernel successfully from USB drive Signed-off-by: Liu Liu <ot_liu.liu@mediatek.corp-partner.google.com> Change-Id: I3f77d116033338f979d14ce34ddf03e00d024e5d Reviewed-on: https://review.coreboot.org/c/coreboot/+/87022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
* soc/mediatek/common: Move DRAMC function declarations to common headerVince Liu2025-04-096-26/+5
| | | | | | | | | | | | | | | To promote code reuse and maintainability, this commit moves the DRAMC parameter function declarations to the common folder. BUG=b:379008996 BRANCH=none TEST=build passed Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com> Change-Id: Iab24f07b4c02da22779ea1c76f3237c144d92b98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/87209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
* soc/mediatek/mt8196: Move TX TRACKING from MT8196 to common folderMike Lin2025-04-094-9/+9
| | | | | | | | | | | | | | | | | | | | The configuration method of the reserved DRAM buffer used for HW TX TRACING on MT8196 is also applicable to other SoCs, such as MT8189. To facilitate reuse, we move the relevant files to the common directory. BUG=b:379008996 BRANCH=none TEST=Reserve memory ok Firmware shows the following log with 12GB DDR board: 00000001ffff0000-00000001ffffffff: RESERVED 000000037fff0000-000000037fffffff: RESERVED Change-Id: I3fdd9d2f7ab1bbdcc097510556929da2134f7d95 Signed-off-by: Mike Lin <mike.lin@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
* soc/mediatek/mt8189: Add DRAM calibration supportMike Lin2025-04-096-21/+197
| | | | | | | | | | | | | | | | | | | | | | | | | Add DRAM calibration support for mt8189. DRAM parameters and related constants are added in dramc_param.h and dramc_soc.h. The common emi.c can be reused for MT8189 as well, so remove the duplicate mt8189/emi.{c,h}. Enable MEDIATEK_DRAM_BLOB_FAST_INIT to allow running DRAM fast calibration via the DRAM blob. BUG=b:379008996 BRANCH=none TEST=Boot up pass and see log 3200 LPDDR5 chan0(x16) rank0: memory test pass 3200 LPDDR5 chan0(x16) rank1: memory test pass 3200 LPDDR5 chan1(x16) rank0: memory test pass 3200 LPDDR5 chan1(x16) rank1: memory test pass Signed-off-by: Mike Lin <mike.lin@mediatek.corp-partner.google.com> Change-Id: Ia6f6e5afc1f4a2e919243bda0799712cd7b4d01f Reviewed-on: https://review.coreboot.org/c/coreboot/+/87037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
* mb/google/nissa/var/meliks: Replace SPD for RAMID 2 with Samsung K3KL8L80CM-MGCTSeunghwan Kim2025-04-093-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Meliks cannot use Samsung K3KL8L80DM-MGCU memory part since Twin Lake platform can only support memory parts that support 8B mode but this part doesn't support it. So we would replace the usage of RAMID 2 (b'0010) with the SPD for this part which supports 8B mode. - Samsung K3KL8L80CM-MGCT BUG=b:402600450 BRANCH=nissa TEST=FW_NAME=meliks emerge-nissa coreboot Change-Id: I7c05b79ca018f68260e71d4f749ecb8573987358 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87002 Reviewed-by: NyeonWoo Kim Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jayvik Desai <jayvik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* mb/*/*/*.fmd: Start flash at 0Arthur Heymans2025-04-09147-169/+156
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | FMAP should not contain information about the memory map. Done with the following command: "find -name \*.fmd -exec sed -i 's/\(FLASH\).* \(.*\) /\1 \2 /' {} \;" for AMD: All addresses that amdfwtool expects as command line parameter have the ADDR_REL_BIOS (flash address) address_mode setting. One exception is the *_FW_A_POSITION and *_FW_B_POSITION addresses. But amdfwtool checks if memory or flash addresses are passed and converts accordingly. So changing the address from memory -> flash doesn't matter for the resulting binary. Since commit 41a162b7a8e4 ("soc/amd/phoenix/Makefile.inc: Pass APOB_NV address as offset") and therefore since phoenix SOC, APOB_NV is passed as flash offset. But before that the memory ABL always assumed a MMIO address (no matter the address_mode) so we need to add a little quirk for that. tested: boot glinda based mainboard and also check that memory training is still cached successfully in APOB_NV. Change-Id: Iac86ef9be6b14817a65bf3a7ccb624d205ca3f99 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/google/fatcat: Enable FSP_UGOP_EARLY_SIGN_OF_LIFESubrata Banik2025-04-092-1/+2
| | | | | | | | | | | | | | | | | | | | | This patch moves eSOL enablement from the SoC level to the mainboard level. This gives the mainboard the option to not use eSOL if it's not supported. The FSP_UGOP_EARLY_SIGN_OF_LIFE Kconfig option is now enabled for the Fatcat and Felino boards. This option was previously enabled at the SoC level for Pantherlake, but is now being enabled specifically for these mainboards. BUG=b:400550435 TEST=Build the Fatcat and Felino targets. Verify that the eSOL works fine. Change-Id: Ie0cf5b00f75071640475d61420824cb2b89b4103 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87236 Reviewed-by: Pranava Y N <pranavayn@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Jayvik Desai <jayvik@google.com>
* mb/google/fatcat/var/fatcat: Implement barrel jack presence checkSubrata Banik2025-04-093-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | Uses fw_config to check if barrel jack PSU is configured. If `PSU_BJ` is selected, checks hardware presence via `google_chromeec_is_barrel_charger_present()`. Allows 'fatcat' to adapt based on configured power source. Includes: - Adds `variant.c` to ramstage build in `Makefile.mk`. - Adds `PSU` field (`PSU_USBC`: 0, `PSU_BJ`: 1) to `overridetree.cb`. - Includes `ec.h` in `variant.c`. TEST=Boot time savings ~62ms on google/fatcat with PSU=0 (USB-C). Change-Id: I68507034cfbf4caa8e5c2ac9c7bebf758a5a5439 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Jayvik Desai <jayvik@google.com> Reviewed-by: Pranava Y N <pranavayn@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* mb/google/fatcat: Introduce variant-specific barrel jack presence checkSubrata Banik2025-04-092-1/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit introduces a weak function `variant_is_barrel_charger_present()` to allow individual Fatcat variants to specify if they support power-on via a barrel jack. The default implementation of this function returns `false`, reflecting the fact that most Chromebook devices within the Fatcat family primarily use USB-C for power. The `baseboard_devtree_update()` function is updated to use this variant-specific check instead of directly calling `google_chromeec_is_barrel_charger_present()` and checking the board model. This allows for more flexibility in handling barrel jack presence across different Fatcat variants. This change enables specific variants that do support barrel jack power to override the weak function and return `true`, allowing the system to behave accordingly (e.g., skipping power optimization when booting with a barrel charger). TEST=Able to build and boot google/fatcat. Change-Id: I613417be5a59790b8a5e6055957a2f518f4c42df Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87183 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pranava Y N <pranavayn@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Jayvik Desai <jayvik@google.com>
* mb/google/fatcat: Perform early post-memory GPIO configurationSubrata Banik2025-04-091-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit restructures the GPIO configuration for google/fatcat devices as below. - Phase 1: GPIO configuration at pre-memory phase. This phase configures essential GPIOs like WWAN and storage power sequencing, This aligns with the initial power-up requirements of these critical components. - Phase 2: This phase handles GPIO configurations for various peripherals like storage type, audio codec, WiFi, cellular interface (post initial power sequence), SD card slot, touchpad, touchscreen, ISH, PEG/x4 slot wake disable, and fingerprint enable/disable based early in post-memory phase (before MPInit). This phased approach: - Improves power sequencing by ordering GPIO configuration for proper IP power enablement. - Optimizes boot time by performing more GPIO configuration before MPInit and FSP-S, allowing earlier IP stabilization and potentially saving ~20ms during device setup and PCIe scan. `baseboard_devtree_update` remains in `mainboard_init` for baseboard- specific device tree updates. TEST=Boot time improved by ~20ms on google/fatcat. Before: 70:device setup done 1,339,599 (95,023) After: 70:device setup done 1,319,613 (72,381) Change-Id: I9c2e58ae012cad06f8e498c75745efaa9bad4a25 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87191 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jayvik Desai <jayvik@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
* soc/amd/glinda/psp_verstage/Makefile.mk: Fix incorrect syntaxMaximilian Brune2025-04-091-1/+1
| | | | | | | | | | | | | Must have been accidentally happened when copying phoenix to glinda. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I78996cd35085c7649c4952d9b121957c8cedd84b Reviewed-on: https://review.coreboot.org/c/coreboot/+/86865 Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* soc/intel/meteorlake: Add missing minimum D-state for SMBUSSean Rhodes2025-04-091-0/+1
| | | | | | | | | | | | | Fixes: Unknown min d_state for PCI: 00:1f.4 Change-Id: I73f84c09bece297194813202f17666741ad33d3a Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
* mb/starlabs/starbook/tgl: Change SSD Enable GPIO to PLTRSTSean Rhodes2025-04-091-1/+1
| | | | | | | | | | | | Change the SSD Enable GPIO to PLTRST, as having it configure to DEEP, renders the SSD inaccessible on S3 exit as it conflicts with the RTD3 driver. Change-Id: If4a406af13005ba4532091d0c5c75f5198e04ff4 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87213 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/nissa/var/guren: Add touch screen ILIT2901 supportDaniel Peng2025-04-091-0/+20
| | | | | | | | | | | | | | | | | | | | | New Touchscreen function for Guren360 project. Touchscreen panel of MUTTO A153728S1Y(11') /K&D KD116N37-30TE-A002(11')/MUTTO B153797S1Y(12') are the same IC controller for ILITEK device, and set TOUCHSCREEN_ILIT2901 to value "2". BUG=b:406168542 BRANCH=firmware-nissa-15217.B TEST=1. emerge-nissa coreboot chromeos-bootimage 2. Confirm command evtest and touchscreen function is workable. Change-Id: I3435a8852b1fdb897d5f89c580b5f9bfca03dd8e Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com>
* mb/google/nissa/var/dirks: Add ACPI DmaProperty for Ethernet deviceIvy Jian2025-04-091-0/+1
| | | | | | | | | | | | | | | | | | | Add ACPI DmaProperty for Ethernet device to support untrusted PCIe port verification. BUG=b:398872682 TEST=cat /sys/devices/pci0000:00/0000:00:1c.0/0000:01:00.0/untrusted returned 1 Change-Id: I24d5f637f1349aace0fba0640c8e72ffc3401de9 Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87197 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
* cpu/x86: Conditionally invalidate caches based on self-snooping supportSubrata Banik2025-04-092-12/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code currently unconditionally flushes or invalidates the entire cache (using `clflush_region` or `wbinvd`) after loading the SIPI vector for APs and after loading SMM handlers. This commit modifies this behavior to only perform these cache operations if the CPU does *not* support self-snooping. Self-snooping CPUs can maintain cache coherency within the core/ complex more efficiently. CPU with self-snoop enabled does not necessarily need to perform wbinvd to ensure data written to the cache is reflected in main memory. Self-snooping CPUs employ a write-back caching policy, combined with a cache coherence protocol, to manage data writes and ensure consistency between cache and main memory. When the BSP writes the SIPI vector or SMM handlers to memory, other units within the same CPU that might be caching these regions should be aware of the updates through the self-snooping mechanism. A full cache flush or invalidate to ensure cache contains reaches to main memory might be unnecessary and could negatively impact performance. By conditionally performing these cache operations based on `self_snooping_supported()`, we can optimize the boot process for CPUs that have advanced cache coherency features while maintaining correct behavior on older or simpler CPUs. TEST=Boot google/rex, brox and fatcat with this patch. Able to reduce boot time by ~19-25ms. Change-Id: If32439752d0ceaa03b1d81873ea0bc562092e9d5 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87182 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/fatcat/variants/fatcat: Refactor X1 PCIe power enable GPIOSubrata Banik2025-04-092-7/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | The system was failing to boot to the OS when the SD FW config was set to NONE. This was because the X1 PCIe slot power enable (GPP_A08) was being configured in `pre_mem_x1slot_pads` only if the SD FW config was not NONE. This commit moves the configuration of GPP_A08 to the `romstage_gpio_table` and sets it to an initial low state. This ensures that the X1 PCIe slot power is correctly initialized early in the boot process, regardless of the SD FW config. The `pre_mem_x1slot_pads` array and its conditional configuration in `fw_config_configure_pre_mem_gpio` have been removed as they are no longer needed. TEST=Able to boot google/fatcat w/ CBI 0x5c9014 (i.e. SD_NONE) Change-Id: I0f2a2540de30294c30c4f5182dab326a54b4583e Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87154 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Pranava Y N <pranavayn@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/cmn/cpu: Refactor USE_INTEL_FSP_MP_INIT enablement logicSubrata Banik2025-04-091-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Kconfig options `USE_INTEL_FSP_MP_INIT` and `USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI` are mutually exclusive ways for the FSP to handle MP initialization. This commit updates the `default` condition for `USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI` to `y if !USE_INTEL_FSP_MP_INIT`. This ensures that if `USE_INTEL_FSP_MP_INIT` is enabled, `USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI` will default to disabled, preventing potential conflicts in MP initialization. The explicit `depends on !USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI` on `USE_INTEL_FSP_MP_INIT` is no longer strictly necessary due to this change in the default value, but it is kept for clarity and to explicitly state the mutual exclusivity. TEST=Able to choose USE_INTEL_FSP_MP_INIT Kconfig for google/fatcat. Change-Id: I9ecc7b50ed6a6b13c4ccde0a49f50a40b606a848 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87161 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
* mb/var/uldrenite: Configure descriptor for either MBVR or FIVRJohn Su2025-04-083-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since we need to support both MBVR (MotherBoard Voltage Regulator) and FIVR (Fully Integrated Voltage Regulator) in this phase, the FIT setting is initially set to FIVR. This causes MBVR boards to have two voltage sources, potentially triggering OVP and leading to reboots during the boot process. The current build's main source is MBVR, so we want to use fw_config to dynamically adjust MFIT and MBVR with the current phase devices to ensure consistency in client devices settings. Refer to Intel#822618 and set PMC Descriptor Record 7, bit 30 (VCCANA VR Location) accordingly. And then CONFIGURE_DESCRIPTOR is a temporary workaround for the current phase. In the next phase, we will choose a specific setting for implementation. If there are any concerns, we use the board ID to restrict it. BUG=b:404126972 TEST=boot to ChromeOS Change-Id: I337574c8c55889ceb49b9f33625feadb48bd8890 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87033 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
* soc/intel/alderlake: Fix incompatible pointer-to-integer conversionJohn Su2025-04-081-2/+2
| | | | | | | | | | | | | | | | | Call update_descriptor, but the builder detected an incompatible pointer to integer conversion error, so upload CL to fix. BUG=b:404126972 TEST=boot to ChromeOS Change-Id: I1f8f19c6bb4636729ffe7be836c21db9a68d63d0 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87091 Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Jayvik Desai <jayvik@google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
* mb/starlabs/starbook/kbl: Re-add the GPE configurationSean Rhodes2025-04-081-0/+5
| | | | | | | | | | | | | These were previously removed, but doing so, slowed down the brightness keys to approx. 3 seconds. Re-add them to make them instant. Change-Id: I1256b57192d2f8987bb476cbcc7fd7e81f314d6d Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87200 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/starlabs/starbook/cml: Re-add the GPE configurationSean Rhodes2025-04-081-0/+5
| | | | | | | | | | | | | These were previously removed, but doing so, slowed down the brightness keys to approx. 3 seconds. Re-add them to make them instant. Change-Id: I3af197cd995bd947c6e72bf5593fc966c85c3e3a Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* {commonlib, lib}: Add timestamp for early chip initializationSubrata Banik2025-04-082-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit introduces a new timestamp `TS_DEVICE_INIT_CHIPS` to specifically mark the start of the `dev_initialize_chips()` function. Previously, the `TS_DEVICE_ENUMERATE` timestamp was incorrectly associated with the `bs_dev_init_chips` function. This patch corrects this by: - Adding the `TS_DEVICE_INIT_CHIPS` enum and name definition. - Updating `bs_dev_init_chips` in `src/lib/hardwaremain.c` to use `TS_DEVICE_INIT_CHIPS`. - Moving the `TS_DEVICE_ENUMERATE` timestamp addition to the `bs_dev_enumerate` function where device enumeration actually begins. This change provides a more accurate and meaningful timestamp for the early chipset initialization phase. TEST=Able to build and boot google/fatcat. ``` 971:loading FSP-S 836,277 (10,658) 17:starting LZ4 decompress (ignore for x86) 847,297 (11,019) 18:finished LZ4 decompress (ignore for x86) 847,376 (79) 30:early chipset initialization 854,579 (7,203) 17:starting LZ4 decompress (ignore for x86) 863,483 (8,903) 18:finished LZ4 decompress (ignore for x86) 863,490 (6) 17:starting LZ4 decompress (ignore for x86) 875,196 (11,705) 18:finished LZ4 decompress (ignore for x86) 875,237 (41) 954:calling FspSiliconInit 875,344 (107) 955:returning from FspSiliconInit 942,740 (67,396) 962:calling FspMultiPhaseSiInit 942,744 (4) 963:returning from FspMultiPhaseSiInit 1,081,355 (138,610) 31:device enumeration 1,081,708 (352) 40:device configuration 1,085,721 (4,013) 50:device enable 1,091,517 (5,795) ``` Change-Id: Ib6860901c6b1528ec5098fc93240c6e65777642b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87152 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Jayvik Desai <jayvik@google.com>
* mb/google/nissa/var/guren: Add WFC for AZWAVE/AM-3BA5533-B moduleDaniel Peng2025-04-082-2/+14
| | | | | | | | | | | | | | | | | | | | | | New WFC function for Guren360 project. ID of Vendor and Product for AZWAVE/AM-3BA5533-B module are 13d3:5533. 1. Add WFC fw_config setting 2. Used USB2 Port7 for WFC BUG=b:406164678 BRANCH=firmware-nissa-15217.B TEST=1. emerge-nissa coreboot chromeos-bootimage 2. Verified with local build bios via command lsusb for 13d3:5533 and SSFC WFC enable Change-Id: Ia2ab019fe76c503cc669ebf4aa8b3d7ae72269c1 Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Jayvik Desai <jayvik@google.com> Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/protectli/vault_ehl/devicetree.cb: Fix assertion in soc/pmutilMichał Żygowski2025-04-071-3/+3
| | | | | | | | | | | | | | | The SoC code requires for GPE DW config values to be different. Assign the default values of PMC GPIO_CONF register as GPIO GPEs are not used on this platform. Fixes the assertion in soc/intel/elkhartalke/pmutil. TEST=Boot Protectli VP2420 to Ubuntu 24.04. Change-Id: Ibf4a1f52bf970c27d0ca8dd1b1377d6a5e6477f9 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/cwwk: Add CWWK CW-ADLNTB-1C2L-V3.0 board as an adl variantsJulian Intronati2025-04-0712-14/+382
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This board is the CWWK variant based upon Alder Lake with 2 2.5 GbE ports. The variants files structure is inspired by system76/adl/variants structure, adapted for cw-adl-4l-v1.0 board and the new cw-adlnth-1c2l-v3.0 (named according to original bios naming). CPU: Intel N100 or N305 Memory: 1x DDR5-4800 SODIMM (max 16 GB) NIC: 2x Intel I226-V 2.5 GbE Expansion: - M.2 2230 E key - M.2 2280 M key - USB 2.0 header - Fan header External ports: - DC power - 2x Ethernet - 2x HDMI - 2x USB 2.0 Working: - Boots Debian 12 with SeaBIOS and EDK II payloads - Serial port - External USB ports - 1x HDMI - 2x Intel I226 2.5 GbE NICs - M.2 ports - ACPI S3 - Fan (ITE IT8613E) driver IT87 (frankcrawford github fork) Not tested: - The second HDMI - Audio - S0ix (cw-adl-4l-v1.0 said it's not working) - Internal USB ports VBT extracted from vendor UEFI firmware version F2 (2024-06-26 10:26:38) was 100% matching the cw-adl-4l-v1.0, so we kept only one in the tree. Change-Id: Ia0553141b41717b560042de1136d53b9c3cf7a69 Signed-off-by: Julian Intronati <julian.intronati@eho.link> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87027 Reviewed-by: Julian Intronati <julian.intronati@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/amd/*/include/soc/msr.h: Move MSR to common locationNaresh Solanki2025-04-076-92/+29
| | | | | | | | | | | | MSR definition in soc/amd/*/include/soc/msr.h are the same & hence move them to common header src/include/cpu/amd/msr.h Change-Id: Ic0cb54b13320f8a38e70c0a76d9b9a51ba0ea01d Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87124 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/starlabs/starbook/mtl: Change SSD enable GPIO to DEEPSean Rhodes2025-04-071-1/+1
| | | | | | | | | | | Set the SSD enable GPIO to DEEP reset, so that the SSD is powered down in S3. Change-Id: I6cc247e04974d293dfc157a3b459a3fb61e43a7f Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/starlabs/*: Enable DDC for DDIASean Rhodes2025-04-066-6/+6
| | | | | | | | | | | | Enable DDC so that GOP can read the backlight brightness from EDID. This avoids FSP repeatedly trying and failing to read it, and also stops the backlight brightness not being restored correctly in Linux. Change-Id: Ic05ec3cece911f61347bceb82e5798729dcaecfe Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/starlabs/starbook/tgl: Tidy GPIO comments for SATASean Rhodes2025-04-061-2/+3
| | | | | | | | | | This is a non-functional change, and only makes the GPIOs easier to read. Change-Id: Iee7121aef28618c0877c97cf454dc1a279758c21 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/starlabs/starbook/tgl: Correct wireless GPIO groupSean Rhodes2025-04-061-5/+4
| | | | | | | | Change-Id: I6565c3fa3d171625b0d3e538371d53d6449db180 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/starlabs/starbook/tgl: Add comments for eSPI GPIOSean Rhodes2025-04-061-1/+9
| | | | | | | | | | This is a non-functional change, and just makes it easier to read. Change-Id: I89028c87eeab95bf4e7a35471072bb41d02b4e6c Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/starlabs/starbook/tgl: Disconnect unused GPIOsSean Rhodes2025-04-061-14/+14
| | | | | | | | | | These pins are not used, so configure them accordingly. Change-Id: If82741382c113b2f05078e0d24690943c9053421 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/starlabs/starbook/tgl: Move PROCHOT GPIO to PCH groupSean Rhodes2025-04-061-2/+1
| | | | | | | | Change-Id: I3fb4421698df9ca3e9a6067d9054ef10ec103f25 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/starlabs/starbook/tgl: Tidy GPIO comments for the retimersSean Rhodes2025-04-061-6/+5
| | | | | | | | | | This is a non-functional change, and only makes the GPIOs easier to read. Change-Id: I237824415c99bf57e9617a37001383cdda4a38e6 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/starlabs/starbook/mtl: Uncomment eSPI GPIOsSean Rhodes2025-04-061-7/+7
| | | | | | | | | | | These, unlike almost all other Intel platforms, are not configured automatically on reset, so coreboot needs to handle it. Change-Id: Ie013ce1769e61fae1622a9cc1a048229fd9d6944 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/starlabs/starbook/tgl: Remove SSD GPIO quirkSean Rhodes2025-04-061-6/+0
| | | | | | | | | | | This quirk was added to turn of the SSD in S3. This is now handled by the RTD3 driver, so it can be removed. Change-Id: Iaf6364a0957f95411c11e31c8317e1c4ec5c769f Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87166 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/starlabs/starbook/mtl: Remove comments for disconnected GPIOsSean Rhodes2025-04-051-188/+0
| | | | | | | | Change-Id: I24c7529fdf606268d1ed1b838912b6448520d816 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/starlabs/{starbook/adl_n,starlite_adl}: Add missing config for TBT LSX 2Sean Rhodes2025-04-052-2/+2
| | | | | | | | Change-Id: Id7cf723e354a98a760b9535309d1d9a8189d21ad Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87163 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/starlabs/starfighter: Remove duplicate entry for GPP_B13Sean Rhodes2025-04-051-2/+0
| | | | | | | | Change-Id: I8ed1ee8389e5e32ec9ddcefeb2c146281de50adb Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/starlabs/starfighter: Tidy GPIO comments for the retimersSean Rhodes2025-04-051-10/+7
| | | | | | | | | | This is a non-functional change, and only makes the GPIOs easier to read. Change-Id: Ia724e342651e064ca095f9f3f1153d86f0a73a46 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87159 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/starlabs/starfighter: Disconnect PEDET GPIOSean Rhodes2025-04-051-1/+1
| | | | | | | | | | These boards do not support SATA, so this is not needed. Change-Id: Iff9a30cf2e8b65649440b33f850f07d499baa073 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87158 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
generated by cgit v1.2.3 (git 2.46.0) at 2025-04-27 14:59:32 +0000