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* mb/google/brya: Create epic variantYunlong Jia3 days12-0/+813
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Create the epic variant of the nissa reference board by copying the template files to a new directory named for the variant. This variant is a Nirul project,support TWL devices and select BOARD_GOOGLE_BASEBOARD_NISSA. DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) H58G56AK6BX069 1 (0001) K3LKBKB0BM-MGCP 2 (0010) H9JCNNNBK3MLYR-N6E 0 (0000) H9JCNNNCP3MLYR-N6E 3 (0011) BUG=404301972 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_EPIC Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: I09e5f3c28b95ae8ef318b7af1dd8634279345ce0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/87041 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Jayvik Desai <jayvik@google.com>
* mb/google/skywalker: Create variant ObiwanCong Yang3 days2-1/+6
| | | | | | | | | | | | | | | Create the variant Obiwan. BUG=b:406115783 TEST=emerge-skywalker coreboot BRANCH=None Change-Id: Ic3478653cee2906117b69aa7335864a0c7b95b29 Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87397 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/smmstore: allow full flash access for capsule updatesKrystian Hebel3 days4-1/+65
| | | | | | | | | | | | | | | | | | | | | | | With DRIVERS_EFI_UPDATE_CAPSULES enabled and when at least one capsule was found, SMMSTORE SMI handler can use commands with the highest bit (0x80) set to access the whole flash instead of just the SMMSTORE region. The rest of the interface is identical to regular SMMSTORE v2 except for a new call to control full flash access. The added call saves information about the availability of capsules in SMM memory. The call is ignored when run more than once, meaning there should be no way of enabling full flash handling after it was disabled and vice versa. The call should always be made by the firmware to lock further calls, so that an OS could not gain full flash access. This is done on entry to BS_POST_DEVICE after capsules are obtained in BS_DEV_INIT. Change-Id: I7f3dbfa965b9dcbade8b2f06a5bd2ac1345c7972 Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
* Revert "soc/mediatek/mt8196: Specify MTKLIB_PATH for building BL31"Yidi Lin3 days1-6/+0
| | | | | | | | | | | | | | | | This reverts commit 2fdfa504377f0032c6d1c99fb9febcf824a413d3. Reason for revert: libbl31.a is under refactoring. Stop linking to this library before finalizing the binary. This patch will be re-landed when the binary is ready. BUG=b:412560091 Change-Id: Ie2c315141a51f30027414cfe59552cb50f2b52f6 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87414 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/pantherlake: Add new SoC config for Intel Wildcat Lake(WCL)Sowmya Aralguppe4 days1-0/+6
| | | | | | | | | | | | TEST=Compiled and Verified on Wildcat Lake Simulation Platform. Change-Id: Ifd5bb19dd41c9e44b5399f570d4e21f03d5fce18 Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87402 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Pranava Y N <pranavayn@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/fatcat/var/felino: Use GPP_C08 for GPIO_PCH_WPTongtong Pan4 days2-2/+2
| | | | | | | | | | | | | | Use GPP_C08 as the GPIO_PCH_WP. BUG=b:409472563 Test=TEST=wp status update verified by toggling it on and off. Change-Id: I0f6c7c051b2d38a787fe3bb21266a6ef6ebc487b Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87413 Reviewed-by: Pranava Y N <pranavayn@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* sb/intel/bd82x6x/me.h: Add missing definitionsKeith Hui4 days1-0/+2
| | | | | | | | | | | Two ME current working state definitions are missing. They are needed for CB:85413. Get them from intelmetool. Change-Id: Ie163c4b29155e3fd44f0cb3096f825c84da37559 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87394 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/uldrenite: Configure ISH_GP5 GPIOKapil Porwal4 days2-2/+4
| | | | | | | | | | | | | BUG=b:410645679 Change-Id: I25285e7a7ae92a19f8750d30661930c4d6c2e1d2 Signed-off-by: Kapil Porwal <kapilporwal@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87345 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jayvik Desai <jayvik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pranava Y N <pranavayn@google.com> Reviewed-by: Yuval Peress <peress@google.com>
* mb/google/rex: Generate RAM IDsRui Zhou5 days3-0/+3
| | | | | | | | | | | | | | | Generate RAM IDs for K3KL8L80DM-MGCU BUG=b:412237636 BRANCH=None TEST=Run part_id_gen tool without any errors Change-Id: Ie3f87f5920942060e8e9f8fcf34c3124ba79f3da Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87396 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* mainboard/asrock/imb-1222: Enable USB3 port in WWAN slotMaxim Polyakov5 days1-5/+19
| | | | | | | | | | | | TEST=connect Sandisk USB 3.1 flash via converter (M.2 Key-B to USB3.0); boot ubuntu 24.04 and run "Benchmark Partition" in the Disks utility; average read rate = 161.1 MB/s (20 samples/10 MiB). Change-Id: Iba5d1d7c4f8180e3d37348c1c4dafce6f6c68cb4 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/asrock/imb-1222: Update GPIO config using new intelp2mMaxim Polyakov5 days1-1/+98
| | | | | | | | | | | - use intelp2m, 2.5-a48e94c74b version; - add missing VGPIO groups. Change-Id: I351a32962561947296b115af96674a4cd1cb192d Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/imb-1222: Update some GPIOs according to new vendor configMaxim Polyakov5 days1-4/+4
| | | | | | | | | | | The memory dump was done for the 1.80 (2023-04-07) version of the vendor's UEFI. Change-Id: I649e2c3ae715651b5f0eadc9b52e61e4deae77a1 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* drivers/intel/mipi_camera: Rework info print outputMatt DeVillier5 days1-7/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | Fix the INFO print for a mipi camera device: - fix device path type for generic devices - print parent device path and PCI devfn for generic devices - reformat the output for both device types to improve readability before: [INFO ] \_SB.PCI0.IPU0.IPU0: Intel MIPI Camera Device I2C address 00h [INFO ] \_SB.PCI0.I2C3.CAM0: Intel MIPI Camera Device I2C address 010h [INFO ] \_SB.PCI0.I2C3.VCM0: Intel MIPI Camera Device I2C address 0ch [INFO ] \_SB.PCI0.I2C3.NVM0: Intel MIPI Camera Device I2C address 050h after: [INFO ] \_SB.PCI0.IPU0: Intel MIPI Camera Device at PCI 05.0 [INFO ] \_SB.PCI0.I2C3.CAM0: Intel MIPI Camera Device at I2C 0x10 [INFO ] \_SB.PCI0.I2C3.VCM0: Intel MIPI Camera Device at I2C 0x0c [INFO ] \_SB.PCI0.I2C3.NVM0: Intel MIPI Camera Device at I2C 0x50 Change-Id: I5c4a072e35c4e0a14b6df0d5f199c5ffb3d61d32 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* drivers/intel/mipi_camera: Only generate ADR if no HID suppliedMatt DeVillier5 days1-3/+2
| | | | | | | | | | | | It's an ACPI spec violation for a device to have both an _ADR and a _HID method, so prefer the latter if a HID value is specified via the chip registers. Change-Id: I5d84dbea52595e61df56a5ff779d5e0ee0d84bdf Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87248 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/erying/tgl: fsp_params: Replace half_populated with statementAlicja Michalska5 days1-3/+1
| | | | | | | | | | It looks neater, but does the same exact thing. Change-Id: Id02ba24ec0295cd4621c69079d719d3df36e6499 Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87362 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8196: Move SPM loader functions to common partmtk176646 days3-82/+87
| | | | | | | | | | | | | | | | To promote code reuse and maintainability, move SPM loader functions to common/spm_v2.c. BUG=b:379008996 BRANCH=none TEST=build passed Signed-off-by: Kun Lu <kun.lu@mediatek.corp-partner.google.com> Change-Id: I20de8662d17e3dbedd84f267f2be7d5d62356ecd Reviewed-on: https://review.coreboot.org/c/coreboot/+/87340 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tree: remove duplicated includesElyes Haouas7 days10-11/+0
| | | | | | | | | Change-Id: Iaf10e1b9fb8ce51605a75ec0a92ee33924c42aa6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jayvik Desai <jayvik@google.com> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
* soc/amd/common/cpu/noncar: Compute core info boost freq & L3 cacheNaresh Solanki8 days1-0/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | On SoCs like Glinda, CPU cores may exhibit slight variations in maximum boost frequency, and the L3 cache can be composed of multiple blocks with different sizes and unique IDs. Add helper functions, 1. get_max_boost_frequency() to compute max boost frequenncy. 2. ap_stash_core_info() to update core_info struct with max boost frequency & all L3 cache block uniq ID & its size. To accurately determine the total L3 cache size: 1. Retrieve L3 cache information for each CPU core. 2. Identify the unique cache ID associated with each core. 3. Aggregate cache sizes for all unique cache IDs to compute the total L3 cache size, ensuring correct summation when L3 cache blocks have different sizes. TEST=Build for Glinda SoC, with L3 cache = 16MB + 8MB. Ran command 'dmidecode -t 7' & verified L3 cache is 24MB(Previously it was wrongly reported as 32MB). Change-Id: I46947e8ac62c903036a81642e03201e353c3dac6 Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85640 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/uldrenite/gpio: Enable ISH sensor interruptsYuval Peress8 days2-4/+8
| | | | | | | | | | | | Enable the interrupts coming from the sensors into the ISH. BUG=b:410645679 Change-Id: I2acaed1900e248cfe7fcc81201c6991a9741f26c Signed-off-by: Yuval Peress <peress@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87333 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/fatcat: Create kinmen variantDavid Wu8 days13-0/+695
| | | | | | | | | | | | | | | | | | | | Create the kinmen variant of the fatcat reference board by copying the fatcat files to a new directory named for the variant. BUG=b:409148565 TEST=1. util/abuild/abuild -p none -t google/fatcat -x -a make sure the build includes GOOGLE_KINMEN 2. Run part_id_gen tool without any errors Change-Id: I51e388e61f102216f6ce9233c87c1915596602be Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87317 Reviewed-by: Bob Moragues <moragues@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jayvik Desai <jayvik@google.com>
* mb/google/brya/var/uldrenite: Use FW_CONFIG for ISHKapil Porwal8 days2-0/+17
| | | | | | | | | | | | | | | | Control ISH device and corresponding GPIOs using a FW_CONFIG field. BUG=b:410645679 TEST=Enable/Disable ISH using the new FW_CONFIG field. Change-Id: I69805116722535d77c7fd7701df261e0faa9138f Signed-off-by: Kapil Porwal <kapilporwal@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jayvik Desai <jayvik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Yuval Peress <peress@google.com>
* mb/asrock/imb-1222: Remove comments for non-functional padsMaxim Polyakov8 days1-41/+41
| | | | | | | | Change-Id: I00a9ab77a9b4ea9b42a50fceffdde382241b6950 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* soc/intel/cnvi: Add HotPlugSupportInD3 PropertySean Rhodes8 days1-3/+12
| | | | | | | | | | | | | | | | Add a DSD with the HotPlugSupportInD3, as when it RTD3, the device will appear as not-present. This will cause Windows to constantly try to enable it, causing an endless loop of the device becoming visible. Test=build and boot `starlabs/starlite_adl`, check CNVi is always visible in device manager. Change-Id: I598ab173074522e9d5af002782c5d3ec7691a815 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87325 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/usb/intel_bluetooth: Add HotPlugSupportInD3 DSD PropertySean Rhodes8 days1-0/+17
| | | | | | | | | | | | | | | | Add a DSD with the HotPlugSupportInD3, as when it RTD3, the device will appear as not-present. This will cause Windows to constantly try to enable it, causing an endless loop of the device becoming visible. Test=build and boot `starlabs/starlite_adl`, check Bluetooth is always visible in device manager. Change-Id: I51a2c764ebe8b98b137eb0c98cfdcf2de6f4b86c Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87324 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/cnvi: Replace _PRx methods with _S0W objectSean Rhodes8 days1-38/+5
| | | | | | | | | | | | | | | | | | | The previous implementation used _PS0 and _PS3 methods to control the device power states. These are now replaced by a _S0W object to better align with both coreboot's existing RTD3 driver, and the examples in the ACPI specification. This ensures that the Bluetooth device is recognized as capable of reaching D3Hot when the system is in S0. Test=build and boot starlite_adl with Windows and Linux, check Bluetooth is functional and power draw decreases ~0.4W with no devices connected. Change-Id: I6762b4a2a2454d4e4de2b25e3e5db17df5a8fc63 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* drivers/usb/intel_bluetooth: Replace _PRx methods with _S0W objectSean Rhodes8 days1-26/+5
| | | | | | | | | | | | | | | | | | | The previous implementation used _PS0 and _PS3 methods to control the device power states. These are now replaced by a _S0W object to better align with both coreboot's existing RTD3 driver, and the examples in the ACPI specification. This ensures that the Bluetooth device is recognized as capable of reaching D3Hot when the system is in S0. Test=build and boot starlite_adl with Windows and Linux, check Bluetooth is functional and power draw decreases ~0.4W with no devices connected. Change-Id: I8aa49ee2220ba2ea39b343ea9a9486fca9f5f3d5 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87241 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/cnvi: Skip calling _ON when device is already enabledSean Rhodes8 days1-0/+14
| | | | | | | | | | | | | | | | Add a check in the _ON method, similar to coreboot's ONSK handling in its RTD3 driver, to determine whether the enable GPIO is already asserted. This prevents the OS from repeatedly invoking _ON, which can happen because CNVi takes around 300ms to initialize after the GPIO is enabled. Change-Id: I53986aa11714666c12056460aa47396266a00a1c Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* drivers/usb/bluetooth: Skip calling _ON when device is already enabledSean Rhodes8 days1-1/+14
| | | | | | | | | | | | | | | | Add a check in the _ON method, similar to coreboot's ONSK handling in its RTD3 driver, to determine whether the enable GPIO is already asserted. This prevents the OS from repeatedly invoking _ON, which can happen because USB Bluetooth takes around 200ms to initialize after the GPIO is enabled. Change-Id: I424bc5f4c5b990fd5cb54daa3d6207828386c6f2 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87239 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drv/wifi/generic: Drop guard for cnvi_gpio_enable registerMatt DeVillier8 days1-2/+0
| | | | | | | | | | | | | Guarding the existence of this register isn't necessary since we guard its usage as well, and it complicates some subsequent changes, so drop it. Change-Id: I557c400e6dffeb9dc5b4b67a6cc6f15ba0ef27d0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87343 Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* soc/intel/cnvi: Correct value of CNVI_ABORT_PLDRSean Rhodes8 days1-2/+2
| | | | | | | | | | | | | | | The definitions were reversed, as PCH_S should use 0x44, and all others 0x80. These values can be seen in SlimBootloader, and most UEFI firmwares. Change-Id: Ia2e3866ef7d0756220f15a8d2bdf639ac6667738 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87323 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
* soc/amd: add functions to retrieve I3C controller infoFelix Held8 days13-0/+88
| | | | | | | | | | | | | | | | Similarly to how things are done for the I2C controller configuration, implement the 'soc_get_i3c_ctrlr_info' function in all SoCs that have I3C controllers. This function returns the contents of the SoC's 'i3c_ctrlr' array containing the base addresses and ACPI names of the I3C controllers. This function will eventually be called by the common I3C code which will be implemented in future patches. Change-Id: Ib23fd896925770f49e567324bc8d12ac4c0944bd Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87280 Reviewed-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/starlabs/starfighter: Remove comments for disconnected GPIOsSean Rhodes8 days1-145/+0
| | | | | | | | Change-Id: Ia609053b61937a2da01e99b13adb4b964f3ae2ad Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87165 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/starlabs/starfighter: Disconnect unused GPIOsSean Rhodes8 days1-4/+4
| | | | | | | | | | These GPIOs are not used, so configure them accordingly. Change-Id: I4e58a0e7545167db2c4034499bb99d3bfffc2277 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87164 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/starlabs/starfighter: Reconfigure PCH Strap GPIOsSean Rhodes8 days1-24/+11
| | | | | | | | | | | | | Configure all strap GPIOs as outputs, rather than some being not connected. This doesn't change anything, but is more explicit. Set these all to sample on RSMRST. Change-Id: I3f7133666743b8aa0dc39df54ffe3483a1ddd605 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87162 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* treewide: Assume FMAP_SECTION_FLASH_START = 0Maximilian Brune8 days7-22/+5
| | | | | | | | | | | | | | Now that we require the FMAP to start at offset 0 in the flash, we can assume this across the entire codebase and therefore simplify it on several ends. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Ieb1a23f9c0ae8c0e1c91287d7eb6f7f0abbf0c2c Reviewed-on: https://review.coreboot.org/c/coreboot/+/86771 Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
* include/fmap.h: Require FMAP_SECTION_FLASH_START == 0Maximilian Brune8 days1-0/+5
| | | | | | | | | | | | | | | | For simplicity we are going to impose this restriction to coreboot. Note however that this is only a restriction for coreboot itself. The FMAP tool itself is still a generic tool that does not require the FMAP to start at offset 0. Add an defacto empty fmap_config.h to our test cases, since fmap.h now includes fmap_config.h. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Iba04ebdcd5557664a865d2854028dd811f052249 Reviewed-on: https://review.coreboot.org/c/coreboot/+/86770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
* soc/mediatek/mt8196: Add DCC driver support in ramstageJarried Lin9 days4-0/+41
| | | | | | | | | | | | | | | | | | | | | Duty Cycle Correlation (DCC) analyzes and optimizes the relationship between the duty cycles of multiple signals. This commit implements DCC driver support to improve clock signals, power management, and communication systems, enhancing system stability and performance. These improvements will become more significant as the SoC ages. BUG=b:389784352 BRANCH=rauru TEST=Build pass, check dcc log: [DEBUG] [DCC] DSU=0x0, LCPU=0x0, MCPU=0x17, BCPU=0x1b Change-Id: I77e5cd951f45dad7a6e2e77c135b821e4179e019 Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87320 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/common: Convert mt6359p_read_field() to a general APIZhigang Qin9 days2-1/+2
| | | | | | | | | | | | | | | | Make mt6359p_read_field() a general API usable by multiple drivers, instead of a static function limited to the original driver. BUG=b:379008996 BRANCH=none TEST=build pass Signed-off-by: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com> Change-Id: I2d9c3de9ad08f918a84fa63c1e9b3af7adc5974a Reviewed-on: https://review.coreboot.org/c/coreboot/+/87336 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/google/skywalker: Enable USB3_HUB_RSTCong Yang9 days2-0/+10
| | | | | | | | | | | | | | | | | | We have to reset the USB hub as early as possible. Otherwise the USB3 hub may not be usable in the payload. This design has been introduced since Cherry. BUG=b:390357201 BRANCH=none TEST=detect USB devices in depthcharge, and the log is like "Added USB disk 2." Change-Id: I4ee24aef2a887c8a30738912a8bf90f830a72bed Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87348 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/google/skywalker: Pass XHCI_INIT_DONE to the payloadCong Yang9 days2-1/+17
| | | | | | | | | | | | | | | | | Configure GPIO (XHCI_INIT_DONE) as output, so that payloads (for example depthcharge) can assert it to notify EC to enable USB VBUS. BUG=b:390357201 BRANCH=none TEST=detect USB devices in depthcharge, and the log is like "Added USB disk 2." Change-Id: I99760ace3e87626f55c52dc4f8a30bab27cba345 Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8189: Add EINT supportot_chhao.chang9 days3-1/+234
| | | | | | | | | | | | | | | | Add support for configuring GPIO pull settings for external interrupts (EINT). BUG=b:379008996 BRANCH=none TEST=build pass Signed-off-by: ot_chhao.chang <ot_chhao.chang@mediatek.com> Change-Id: I0a8e0a45eb4466d893405684f560b84e7a992630 Reviewed-on: https://review.coreboot.org/c/coreboot/+/87337 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8189: Enable ARM Trusted Firmware integrationVince Liu9 days2-0/+4
| | | | | | | | | | | | | | | | | Enable configuration to build with MT8189 arm-trusted-firmware drivers. BUG=b:379008996 BRANCH=none TEST=build passed. Output coreboot log: [INFO ] CBFS: Found 'fallback/bl31' @0x4e880 size 0x42e9 in mcache @0xffffeb90 Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com> Change-Id: If5c311bea10ad8cb0b8b7a5e48d9e36d0d569a7e Reviewed-on: https://review.coreboot.org/c/coreboot/+/87003 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/common: Remove infracfg.h in pmif_spiZhigang Qin9 days1-1/+0
| | | | | | | | | | | | | | | | Since infracfg.h is not used in pmif_spi.c, remove its inclusion to prevent build errors in projects that don't have infracfg.h. BUG=b:379008996 BRANCH=none TEST=build pass Signed-off-by: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com> Change-Id: I09229ff370a53407b3f0c290704887de367ed80b Reviewed-on: https://review.coreboot.org/c/coreboot/+/87339 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/rauru: Add FORCE_MAX_SWING quirk for ATNA40HQ01-0Yidi Lin9 days7-2/+56
| | | | | | | | | | | | | | | | | | | | | | The flickering issue on ATNA40HQ01-0 panel can be resolved by setting the swing level to the maximum (500mV). Therefore, add FORCE_MAX_SWING quirk for ATNA40HQ01-0 panel where the fw config's OLED_WQXGA_PLUS field is set to PRESENT. As OLED_WQXGA_PLUS is currently only available on Navi, add an overridetree.cb for Navi. BRANCH=rauru BUG=b:392040003 TEST=check edp training pass and show log: [INFO ] fw_config match found: OLED_WQXGA_PLUS=PRESENT ... [INFO ] update_swing_preemphasis: Force swing setting to 3 (500 mV) Change-Id: I4797ef8fe2257a9b578a969794d624d6e0f97d07 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87028 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* mb/google/rex/var/kanix: Configure Acoustic noise mitigationKenneth Chan9 days1-0/+10
| | | | | | | | | | | | | | Enable Acoustic noise mitigation for google/kanix and set slew rate to 1/8 for IA and GT domains. BUG=b:409934780 BRANCH=firmware-rex-15709.B TEST=Able to build and boot to google/kanix Change-Id: I73460715ac71428843cf505a21de15a6e4d15bea Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87349 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/fatcat: Override FSP-M UART MMIO for GFX PEIM debugSubrata Banik9 days1-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch overrides the FSP-M UART MMIO base address to ensure the FSP GFX PEIM can output debug console messages when required. Currently, the default UART MMIO base used by FSP-M/S might not be the intended console UART for debug output in boot stages, particularly for the GFX PEIM. By overriding it with the value derived from `CONFIG_UART_FOR_CONSOLE` when either `PcdSerialDebugLevel` or `SerialDebugMrcLevel` is non-zero, we ensure that debug logs are directed to the configured console. This change is crucial for debugging issues within the GFX PEIM initialization process. BUG=b:380375181 TEST=Verified that enabling FSP debug tokens after this change allows viewing debug output from the GFX PEIM during display initialization. Steps to reproduce: 1. Flash an AP FW image (`image.fatcat.serial.bin`). 2. Observe the absence of debug output from the GFX PEIM during display initialization. 3. Dynamically enable the FSP debug token using ``` sudo cbfstool image-fatcat.serial.bin add-int -i 3 -n option/fsp_pcd_debug_level ``` 4. Flash the modified AP FW image. 5. Observe debug output from the GFX PEIM during display initialization ``` [INFO]:[IsGraphicsDeviceSupported()]... [INFO]:[GetVbtStartAddress()] ``` Change-Id: I835ef75cb3046217127823c92f708bfe4f3ff741 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87318 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Jayvik Desai <jayvik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alok Agarwal <alok.agarwal@intel.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
* soc/intel/alderlake/vr_config: Add Amston Lake X7433REHarrie Paijmans9 days2-0/+20
| | | | | | | | | | | | | | | | | | | Add the Amston Lake (9W) with MCH_ID 0x4674 to the vr_config table. Based on Intel docs 721616 rev 2.3. BUG=NA TEST=Boots on Intel Alder Lake CRB with X7433RE processor Change-Id: I7249d3223ccbb1671a0b84da1c2347737e1aec89 Signed-off-by: Harrie Paijmans <hpaijmans@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87246 Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* mb/google/nissa/var/dirks: correct usb2_ports settingIvy Jian9 days2-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | When re-purposing the TCSS port to USB Type-A, PortResetMessageEnable must be enabled for USB2 ports that are paired with the CPU XHCI port. Set to USB2_PORT_TYPE_C to enable PortResetMessageEnable. Also remove the workaround. (workaround CL:87053) BUG=b:400809281 TEST=Connecting a USB3 speed device,using lsusb -t to check enumerated status. with change: /: Bus 02.Port 1: Dev 1, Class=root_hub, Driver=xhci_hcd/2p, 20000M/x2 |__ Port 2: Dev 2, If 0, Class=Mass Storage, Driver=usb-storage, 5000M without change: /: Bus 03.Port 1: Dev 1, Class=root_hub, Driver=xhci_hcd/12p, 480M |__ Port 2: Dev 4, If 0, Class=Mass Storage, Driver=usb-storage, 480M Change-Id: I7c4743d1d3bcf2567fdca9c0e07ed02c240d4baf Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87301 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* arch/x86: Use defines for GDT segmentsPatrick Rudolph9 days3-6/+9
| | | | | | | | | | | Stop using magic values and use defines for Global Descriptor Table (GDT) offsets. Use the existing defines from the corresponding headers. Change-Id: I40c15f6341bdef9cd457619ec81e7ac624ec2d63 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87254 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/common/display: Add force max swing quirkYidi Lin9 days4-1/+19
| | | | | | | | | | | | | | | | | | | | | | | A 'quirks' variable is added for panels that require special handling in the display driver due to sensitivity to the eDP signal quality. The display driver can then handle the special requests accordingly. On Navi, the swing level needs to be increased to 3 (500mV) for the ATNA40HQ01-0 panel to resolve a flickering issue. BRANCH=rauru BUG=b:392040003 TEST=check edp training pass and show log: [INFO ] fw_config match found: OLED_WQXGA_PLUS=PRESENT ... [INFO ] update_swing_preemphasis: Force swing setting to 3 (500 mV) Signed-off-by: Bincai Liu <bincai.liu@mediatek.corp-partner.google.com> Signed-off-by: Yidi Lin <yidilin@chromium.org> Change-Id: Ifa8c45050f61d3dff1fa7aed8fa8e435391a6f3a Reviewed-on: https://review.coreboot.org/c/coreboot/+/86999 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
generated by cgit v1.2.3 (git 2.46.0) at 2025-04-26 19:36:37 +0000