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* util/spd_tools/spd_gen/lp5: Remove maxSpeed for SabrinaKarthikeyan Ramasubramanian2022-08-011-12/+0
| | | | | | | | | | | | | | | Firmware component that does memory training already limits the memory controller to train at 5500 Mbps for all memory parts in Sabrina. Hence removing this interim SPD change to limit the speed. BUG=b:238074863 TEST=Build and boot to OS in Skyrim. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I2bc82c7407a97aac282708c3e0bd56ae99a8fc31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66290 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/spd_tools: Limit memory speed to 5500 Mbps for SabrinaKarthikeyan Ramasubramanian2022-07-191-5/+17
| | | | | | | | | | | | | | In Sabrina platform, memory speed is limited to 5500 Mbps. Update the SPD generation tool to limit to that speed. BUG=b:238074863 TEST=Build and boot to OS in Skyrim. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ie3507898167012e0d812c9b1aacba72e9055fcd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* util/spd_tools: Add support for 7500 MT/s lp5 modulesJack Rosenthal2022-07-141-0/+5
| | | | | | | | | | | | | | | | | | spd_tools does not support LP5x modules yet, and the easiest way to do this is to add support for 7500 MT/s in lp5.go (reference the comments on CB:65063). BUG=b:238674174 BRANCH=firmware-brya-14505.B TEST=With follow-on CL, run: util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I1558d69bc6f28c02c20aa9cd87d4543c1cf52afd Reviewed-on: https://review.coreboot.org/c/coreboot/+/65794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
* util/spd_tools: Add Intel Meteor Lake (MTL) platformSubrata Banik2022-07-143-1/+4
| | | | | | | | | | | | | | This patch add support for MTL platform to the `spd_tools`. This would be useful to create dynamic SPD for rex variants. BUG=b:224325352 TEST=Able to generate SPD for LP5 DRAM part. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I1db6e3a63d2842c12ef0f256ba1d32b9258670f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
* util/spd_tools/part_id_gen: Support Sabrina SoCKarthikeyan Ramasubramanian2022-04-141-0/+1
| | | | | | | | | | | | | | Add support to generate DRAM part ID for boards using Sabrina SoC. BUG=None TEST=Generate DRAM part ID for Skyrim mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ica57b12239019831f7bf93982be3c93b7f8b6986 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* util/spd_tools: Add ability to override SPD file for partsRobert Zieba2022-04-052-27/+64
| | | | | | | | | | | | | | | This commit adds the ability to override the SPD file that is used for a specific part. BUG=b:224884904 TEST=Verified that generated makefile uses specified SPD file and that it remains unchanged when this capability is not used Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I078dd04fead2bf19f53bc6ca8295187d439adc20 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63281 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
* util/spd_tools: Add support for exclusive IDsRobert Zieba2022-03-222-17/+62
| | | | | | | | | | | | | | | | | Currently memory parts that use the same SPD are assigned the same ID by spd_tools. This commit adds support for exclusive IDs. When given an exclusive ID a memory part will not share its ID with other parts unless they also have the same exclusive ID. BUG=b:225161910 TEST=Ran part_id_gen and checked that exclusive IDs work correctly and that the current behavior still works in their abscence. Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: Ife5afe32337f69bc06451ce16238c7a83bc983c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62905 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* util/spd_tools: Encode SDRAM min cycle time (TCKMinPs)Karthikeyan Ramasubramanian2022-03-081-10/+36
| | | | | | | | | | | | | | | ADL encodes CK cycle time as tCKMin whereas Sabrina encodes WCK cycle time. Encode tCKMin as per the respective advisories. BUG=None TEST=Generate the SPD and ensure that tCKMin is encoded accordingly. Minimum CAS Latency time is also impacted and is encoded accordingly. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I99ada7ead3a75befb0f934af871eecc060adcb26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
* util/spd_tools/spd_gen/lp5: Encode Bank ArchitectureKarthikeyan Ramasubramanian2022-02-171-19/+106
| | | | | | | | | | | | | | | | ADL supports 8B Bank Architecture, whereas Sabrina supports either BG or 16B Bank Architectures depending on the speed. This influences SDRAM Density and Banks, SDRAM Addressing bytes in SPD. Encode them as per the individual SoC advisories. BUG=b:211510456 TEST=Generate SPDs for Sabrina. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ic854ccccb2b301e75d0f28cd36daf87fd41e07e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61948 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* util/spd_tools/spd_gen/lp5: Encode Optional SDRAM featuresKarthikeyan Ramasubramanian2022-02-171-34/+69
| | | | | | | | | | | | | | | | | ADL and Sabrina provide different advisories to encode Optional SDRAM features (byte indices 7 & 9). Encode those bytes as per the respective advisories. BUG=b:211510456 TEST=Generate the SPD binaries for Sabrina. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Icac8ae148458162768a919d9690d7bf96734e6c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* util/spd_tools/spd_gen/lp5: Update BusWidth EncodingKarthikeyan Ramasubramanian2022-02-081-9/+28
| | | | | | | | | | | | | | ADL and Sabrina have different advisory regarding encoding the bus width. Encode the bus width as per the respective advisories. BUG=b:211510456 TEST=Build spd_gen and ensure that the bus width is encoded as expected. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ia12a5bd8f70a70ca8a510ecf00f6268c6904ec25 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* util/spd_tools/spd_gen: Add support for Sabrina SoCKarthikeyan Ramasubramanian2022-02-072-3/+32
| | | | | | | | | | | | | | | | | | | | | Add support to generate SPD binary for Sabrina SoC. Mainboards using Sabrina SoC are planning to use LP5 memory technology. Some of the SPD bytes expected by Sabrina differ from the existing ADL. To start with, memory training code for Sabrina expects SPD Revision 1.1. More patches will follow to accommodate additional differences. BUG=b:211510456 TEST=make -C util/spd_tools. Generate SPD binaries for the existing memory parts in lp5/memory_parts.json and observe that SPDs for Sabrina is generated as a separate set without impacting the ADL mainboards. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I2a2c0d0e8c8cbebf3937a99df8f170ae8afc75df Reviewed-on: https://review.coreboot.org/c/coreboot/+/61542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* util/spd_tools: Document adding support for a new memory technologyReka Norman2021-11-092-0/+72
| | | | | | | | | | | | | | | | | Add documentation describing how to add support for a new memory technology to spd_tools: - Add a section to the README. - Document the memTech interface in spd_gen.go. BUG=b:191776301 TEST=None Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Ie710c1c686ddf5288db35cf43e5f1ac9b1974305 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59005 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/spd_tools: Add LP5 support for ADLReka Norman2021-11-044-6/+726
| | | | | | | | | | | | | | | | | | | | | Add LP5 support to spd_tools. Currently, only Intel Alder Lake (ADL) is supported. The SPDs are generated based on a combination of: - The LPDDR5 spec JESD209-5B. - The SPD spec SPD4.1.2.M-2 (the LPDDR3/4 spec is used since JEDEC has not released an SPD spec for LPDDR5). - Intel recommendations in advisory #616599. BUG=b:201234943, b:198704251 TEST=Generate the SPD and manifests for a test part, and check that the SPD matches Intel's expectation. More details in CB:58680. Change-Id: Ic1e68d44f7c0ad64aa9904b7e1297d24bd5db56e Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* util/spd_tools: Remove old lp4x and ddr4 versions of spd_toolsReka Norman2021-09-239-4115/+0
| | | | | | | | | | | | | | | The migration to the new unified version of spd_tools is complete, so the old lp4x and ddr4 versions can be removed. BUG=b:191776301 TEST=None Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I6b1fc297739efc8dc7d7eec64956bf3343984604 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* util/spd_tools: Sort platforms_manifest entries by set numberReka Norman2021-09-231-3/+10
| | | | | | | | | | | | | | | Ensure that the order of entries in each platform manifest is consistent every time spd_gen is run. BUG=b:191776301 TEST=Run spd_gen for lp4x and ddr4, check that the manifests are unchanged. Change-Id: I7bfea65c8fc781df80a8725c0cf20c7547c857e8 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* util/spd_tools: Remove PLK platformReka Norman2021-09-233-4/+1
| | | | | | | | | | | | | | | Currently spd_tools treats PCO and PLK as separate platforms. This is unnecessary since they have the same SPD requirements. Remove PLK, and use PCO as the platform for all zork variants. BUG=b:191776301 TEST=None Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I7eeeab53fb3e0d92c3675fb80b4747297d4257ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/57771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* util/spd_tools: Add README for unified spd_toolsReka Norman2021-09-231-0/+495
| | | | | | | | | | | | | | | | Combine the existing lp4x and ddr4 READMEs into a single file, and update it to reflect the new unified version of the tools. BUG=b:191776301 TEST=None Change-Id: I866932a1d0b5b6b47b0daff893b37de7a302b4e6 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* util/spd_tools: Add 'Generated by' string to part_id_gen output filesReka Norman2021-09-211-6/+10
| | | | | | | | | | | | | | | Add a 'Generated by' string to the generated Makefile.inc and dram_id.generated.txt, showing the command used to generate the files. BUG=b:191776301 TEST=Run part_id_gen, check that the generated files contain the string Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Ic9a7826212a732288f36f111b7bc20365a1f702d Reviewed-on: https://review.coreboot.org/c/coreboot/+/57692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
* util/spd_tools: Automatically determine the SPD dir in part_id_genReka Norman2021-09-211-20/+117
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, one of the arguments to part_id_gen is the directory containing the SPD files, e.g. spd/lp4x/set-0. This requires the user of the tool to understand the spd/ directory structure, and manually look up the set number corresponding to their platform. Change part_id_gen to take the platform and memory technology as arguments instead of the SPD directory, and automatically determine the SPD directory by reading the platforms manifest file generated by spd_gen.go. BUG=b:191776301 TEST=Run part_id_gen and check that the generated Makefile.inc and dram_id.generated.txt are the same as before. Example: util/spd_tools/bin/part_id_gen \ ADL \ lp4x \ src/mainboard/google/brya/variants/kano/memory \ src/mainboard/google/brya/variants/kano/memory/mem_parts_used.txt Change-Id: I7cd7243d76b5769e8a15daa56b8438274bdd8e96 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* util/spd_tools: Add max ID check for auto-generated IDs to part_id_genReka Norman2021-09-211-0/+3
| | | | | | | | | | | | | | | | Currently, the maximum part ID of 15 is enforced only for manually assigned IDs. Also enforce it for automatically assigned IDs. BUG=b:191776301 TEST=part_id_gen fails when the number of part IDs which would be assigned is greater than MaxMemoryId. Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I802190a13b68439ccbcdb28300ccc5fd1b38a9c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57691 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* util: Add DDR4 generic SPD for 4JQA-0622ADFrank Wu2021-09-211-0/+11
| | | | | | | | | | | | | | | Add SPD support for DDR4 memory part BUG=b:199469240 TEST=none Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Ie67cf6b90304f0bcf80838866c7461c0cea86dc3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* util/spd_tools: Implement a unified version of the part_id_gen toolReka Norman2021-09-202-1/+315
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently there are two versions of gen_part_id.go, one for LP4x and one DDR4. This change implements a unified version of this tool. The new part_id_gen.go is almost identical to the existing ddr4/gen_part_id.go. The new version was based on the ddr4 version and not the lp4x version, since the ddr4 version contains extra logic to support fixed IDs in the mem_parts_used files. The only non-trivial change from ddr4/gen_part_id.go is to include the full paths of SPD files in the generated Makefile.inc. E.g. instead of SPD_SOURCES += lp4x-spd-1.hex the full path relative to the coreboot root directory is included: SPD_SOURCES += spd/lp4x/set-0/spd-1.hex BUG=b:191776301 TEST=For each variant of brya/volteer/dedede/guybrush/zork, run part_id_gen and verify that the generated Makefile.inc and dram_id.generated.txt are identical to those currently in the src tree, except for the modified SPD file paths in Makefile.inc. Example: util/spd_tools/bin/part_id_gen \ spd/lp4x/set-0 \ src/mainboard/google/brya/variants/kano/memory \ src/mainboard/google/brya/variants/kano/memory/mem_parts_used.txt Change-Id: Ib33d09076f340f688519dae7956a2b27af090c0b Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* util/spd_tools: Implement a unified version of the spd_gen toolReka Norman2021-09-175-0/+2483
| | | | | | | | | | | | | | | | | | | | | | | | | | Currently there are two versions of spd_tools: one for LP4x and one for DDR4. This change is the first step in unifying these into a single tool. This change implements a unified version of the spd_gen tool, by combining the functionality currently in lp4x/gen_spd.go and ddr4/gen_spd.go. The unified version takes the memory technology as an argument, and generates SPD files for all platforms supporting that technology. BUG=b:191776301 TEST=Compare the SPDs generated by the old and new versions of the tool for all supported platforms. For reference, the test script used is here: https://review.coreboot.org/c/coreboot/+/57511 Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I7fc036996dbafbb54e075da0c3ac2ea0886a6db2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57512 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* util/spd_tools/lp4x: Update READMETim Wawrzynczak2021-08-091-9/+10
| | | | | | | | | | | The lp4x spd_tools also support Alder Lake (ADL), so update the the README to reflect this fact. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Iedb1ea1c3558e5f179feac2c725667db5b327b2e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56857 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/spd_tools/lp4x: Add new memory parts and generate SPDsDavid Wu2021-07-281-0/+48
| | | | | | | | | | | | | | | | | | | This change adds the following memory parts to LP4x global list and generates SPDs using gen_spd.go for ADL: 1. H54G46CYRBX267 2. H54G56CYRBX247 3. K4U6E3S4AB-MGCL 4. K4UBE3D4AB-MGCL BUG=b:194686484 b:194765811 TEST=build. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: If85088f843ab11cc531a3975b5cac3e36b573970 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* util: Add DDR4 generic SPD for MT40A512M16TB-062E:RWisley Chen2021-06-141-0/+11
| | | | | | | | | | | | | Add SPD support for DDR4 memory part BUG=b:190020997 TEST=none Change-Id: I423131cb674e1e5ec699c7a28e5b5e6746247b2a Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55164 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/spd_tools: Modify MT53E1G32D2NP-046 WT:B LPDDR4 configAmanda Huang2021-06-031-1/+1
| | | | | | | | | | | | | | | | CB:52586 ("util/spd_tools: Add MT53E1G32D2NP-046 WT:B LPDDR4 config") incorrectly set ranks per channel to 1. However, MT53E1G32D2NP-046 WT:B part has 2 channels per die and 2 physical dies. Each channel in each die shares DQ-DQS lines with the channel in other die and uses separate CS lines. Thus, number of ranks per channel is 2. This change fixes the attribute ranksPerChannel for MT53E1G32D2NP-046 WT:B in LP4x global config by setting it to 2. BUG=b:186616388 Change-Id: Iba87754ca04c2e026a9cbc8ef07412b467140cba Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* util/spd_tools/lp4x: Add new memory part to to global memory definitionDtrain Hsu2021-05-221-0/+12
| | | | | | | | | | | | | This new definition is for MT53E512M32D1NP-046 WT:B used on Cret. BUG=b:183057749 TEST=Generate SPDs Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Ica5df61d96d2c4cbe62a560a53bd3bd08eb121f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* util/spd_tools: Add MT53E1G32D2NP-046 WT:B LPDDR4 configMartin Roth2021-04-231-0/+12
| | | | | | | | | | | | | | | The revision B version of the MT53E1G32D2NP-046 memory chip will be used in the next guybrush build. It has a different internal layout than the Revision A part, with 2 ZQ lines per module instead of 1. BUG=b:186027256 TEST=Build only Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I066f40eb890648a9be17cfe0cee20d299000c11a Reviewed-on: https://review.coreboot.org/c/coreboot/+/52586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* util: Add DDR4 generic SPD for Micron MT40A1G16RC-062E-B 16GbKevin Chiu2021-04-061-1/+13
| | | | | | | | | | | | | Add SPD support for Micron DDR4 memory part MT40A1G16RC-062E-B 16Gb BUG=b:184024142 TEST=none Change-Id: I438310fb74d96953bc83374df3109e4c56192a5f Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
* util: Add DDR4 generic SPD for H4AAG165WB-BCWENick Vaccaro2021-03-221-1/+13
| | | | | | | | | | | | | Add SPD support for DDR4 memory part H4AAG165WB-BCWE. BUG=b:181732562 TEST=none Change-Id: I923fcbd08875a2a581fba4b1db00a4d1c1bb11cf Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51666 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util: Add new memory part to LP4x listAmanda Huang2021-03-031-0/+12
| | | | | | | | | | | | | | | | | Add memory part MT53E2G32D4NQ-046 to LP4x global list. Attributes are derived from data sheets.Also, regenerate the SPD files for ADL SoC using the newly added parts. BUG=b:181378727 TEST=Compared generated SPD with data sheets and checked in SPD Change-Id: Ic06e9d672a2d3db2b4ea12d15b462843c90db8f6 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* util/spd_tools/lp4x: Add 2 new parts to global memory definitionMartin Roth2021-03-031-0/+26
| | | | | | | | | | | | | | | This adds the definitions for MT53E1G32D4NQ-046 WT:E used on Majolica, and the NT6AP256T32AV-J1 part used on Guybrush. BUG=b:178715165 TEST=Generate SPDs Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I7cd729fc72d8f44a449429e97683b2ca1f560f2c Reviewed-on: https://review.coreboot.org/c/coreboot/+/51057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
* util/spd_tools: Run go fmt on all .go filesMartin Roth2021-02-274-333/+330
| | | | | | | | | | | | | | | This just reformats these files. go fmt should probably be run on the check-in of every .go file. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I70ced115bad42d123474b18bbff2e4c0a16f3d88 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51019 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/spd_tools: Add Cezanne support to lp4x/gen_spd.goMartin Roth2021-02-271-4/+13
| | | | | | | | | | | | | | | | | To supply memory information for Guybrush, the lpddr4x script for generating SPDs needs to be updated for Cezanne. BUG=b:178722935 TEST=Add the part used on Majolica to the global lpddr4x json file and verify that the output is similar to the actual SPD used for Majolica. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I1f522cb4a92b4fe4c26cad0689437c33ec44befe Reviewed-on: https://review.coreboot.org/c/coreboot/+/51015 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util: Make sure all util dirs have description files at top levelMartin Roth2021-01-041-0/+11
| | | | | | | | | | | | | New util directories have been added with no description.md file. The description file for supermicro was added at a secondary level, which doesn't help a user find the util since no path was added. Move it up to the top level. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I40b4c25dd7706513e96c6b8078a34160f8bb901e Reviewed-on: https://review.coreboot.org/c/coreboot/+/48961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tom Hiller <thrilleratplay@gmail.com>
* util: Modify LPDDR4 spd_tools to generate SPDs for ADL boardsAmanda Huang2020-12-171-6/+7
| | | | | | | | | | | | | | | | Generates de-duplicated SPD files using a global memory part list provided by the mainboard in JSON format. BUG=b:173132516 Change-Id: I4964ec28d74ab36c6b6f2e9dce6c923d1df95c84 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48526 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* lp4x: Add new memory parts and generate SPDsNick Vaccaro2020-11-301-0/+12
| | | | | | | | | | | | | | | | Add MT53D512M64D4NW-046 WT:F memory part to LP4x global list of available LP4x parts and to the global JSON file containing LP4x parts and their characteristics. BUG=b:172993397 TEST=none Change-Id: I09c6eab640c169dbdb451964967d14a31e314496 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
* lp4x: Add new memory parts and generate SPDsDavid Wu2020-11-161-0/+36
| | | | | | | | | | | | | | | | | | | | | | This change adds the following memory parts to LP4x global list of available LP4x parts and to the global JSON file containing LP4x parts and their characteristics. 1. H9HCNNNCRMBLPR-NEE 2. H9HCNNNFBMBLPR-NEE 3. MT53D1G64D4NW-046 WT:A BUG=b:172751925,b:172781673,b:172782100,b:172781562 TEST=cd <path_to_coreboot_src>/util/spd_tools/lp4x && ./gen_spd <path_to_coreboot_src>/src/soc/intel/tigerlake/spd \ global_lp4x_mem_parts.json.txt "TGL" Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I37702770f707fe078920694468552c5db59c478f Reviewed-on: https://review.coreboot.org/c/coreboot/+/47350 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* .gitignore: Ignore .test/.dependencies globallyPatrick Georgi2020-10-311-2/+0
| | | | | | | | | | | These were originally ignored only inside util/ but these files shouldn't be tracked anywhere. Change-Id: Ie0846bd8bdd6e52f420f9dd2e72a8a922102ff90 Signed-off-by: Patrick Georgi <patrick@georgi.software> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* .gitignore: Split into subdirectory filesPatrick Georgi2020-10-301-0/+4
| | | | | | | | | | | | | | There's no need for the global list of files to ignore, so use git's ability to work with more local configuration. Change-Id: I50882e6756cbc0fdfd899353cc23962544690fb3 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46879 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util: Add DDR4 generic SPD for H5ANAG6NCJR-XNCNick Vaccaro2020-10-121-0/+12
| | | | | | | | | | | | | Add SPD support for DDR4 memory part H5ANAG6NCJR-XNC. BUG=b:161772961 TEST=none Change-Id: I71e4de9a28f78bbf8c7de1fcafa3596276a5f2f9 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* Revert "util/spd_tools: output binaries instead of hexdumps"Rob Barnes2020-10-035-39/+47
| | | | | | | | | | | | | | | This reverts commit f23794cf04030bb8d1d7ebe0a3634dffd092e2f7. Reason for revert: This change breaks compatibility if the changes in CB:44775 are not also included. CB:44775 is still under discussion, so revert this change to make spd_tools usable again. Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I5840a1b895dcbc8b91c76d8b60df2f95b93a4370 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44999 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util: Add new memory part for zork boardsAmanda Huang2020-09-281-0/+12
| | | | | | | | | | | | | | Add memory part H5ANAG6NDMR-XNC. Attributes are derived from data sheets. BUG=b:165611994 TEST=Compared generated SPD with data sheets and checked in SPD Change-Id: Ifdcc7536441e9f0b94543c6f06fe466596f752dc Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
* util/spd_tools: Support comments in mem_parts_usedRob Barnes2020-09-091-0/+1
| | | | | | | | | | | | | Allow comments prefixed with '#' in mem_parts_used csv file. BUG=None TEST=Run gen_part_id with mem_parts_used file containing comments Change-Id: Ia9e274d45aa06dea7a3a5f8cd1c8ee2b23398876 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* util/spd_tools: output binaries instead of hexdumpsMichael Niewöhner2020-09-085-47/+39
| | | | | | | | | | | | | | | Instead of generating hexdumps, output binary SPD files since we plan to convert all hex SPD files to binary. Also adjust the file extension where needed. Test: compared generated binaries with converted binaries from hex files Change-Id: Ie99d108ca90758d09dbefad20fe6c9f7fc263ef1 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44878 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* util: Add memory parts needed by zork boardsRob Barnes2020-08-281-0/+144
| | | | | | | | | | | | | | Add memory parts needed by zork boards. Attributes are derived from data sheets. BUG=b:162939176 TEST=Compared generated SPDs with data sheets and checked in SPDs Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I67f205f9af24bbc5c12656be1f363a15fe975955 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44447 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/gen_spd: translate DeviceBusWidth to die bus widthNick Vaccaro2020-08-283-17/+35
| | | | | | | | | | | | | | | | | | | | If a memory part is a x16 part that has two dies and only a single rank, then the x16 describes the part width (since this solution will need to be a stacked solution) and as such, we must translate the DeviceBusWidth to the "die bus width" instead. Change DeviceBusWidth variable name to PackageBusWidth to be more descriptive BUG=b:166645306, b:160157545 TEST=run gen_spd and verify that spds for parts matching description above changed appropriately. Change-Id: Ia6f3ca109d344b7a015da28125a94ce10d2bdfb8 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* Revert "util: update lp4x gen_part_id tool to include memory type"Aaron Durbin2020-08-281-1/+0
| | | | | | | | | | | | This reverts commit eb7a1dd80e72ef435c71650284f355f7f57ebe72. MEMORY_TYPE = lines in Makefiles are not longer needed. Drop it. Change-Id: I96ac39a30555a870e7778a0e71d738407b6b89ef Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44895 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-28 12:21:07 +0000