summaryrefslogtreecommitdiffstats
path: root/src/arch/armv7/exception.c
blob: 1055cb5663c6148a547d626bb8af7540f7d3e39f (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
/*
 * This file is part of the libpayload project.
 *
 * Copyright 2013 Google Inc.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 */

#include <console/console.h>
#include <arch/exception.h>
#include <stdint.h>

void exception_test(void);

static int test_abort;

void exception_undefined_instruction(uint32_t *);
void exception_software_interrupt(uint32_t *);
void exception_prefetch_abort(uint32_t *);
void exception_data_abort(uint32_t *);
void exception_not_used(uint32_t *);
void exception_irq(uint32_t *);
void exception_fiq(uint32_t *);

static void print_regs(uint32_t *regs)
{
	int i;
	/* Don't print the link register and stack pointer since we don't have their
	 * actual value. They are hidden by the 'shadow' registers provided
	 * by the trap hardware.
	 */
	for (i = 0; i < 16; i++) {
		if (i == 15)
			printk(BIOS_ERR, "PC");
		else if (i == 14)
			continue; /* LR */
		else if (i == 13)
			continue; /* SP */
		else if (i == 12)
			printk(BIOS_ERR, "IP");
		else
			printk(BIOS_ERR, "R%d", i);
		printk(BIOS_ERR, " = 0x%08x\n", regs[i]);
	}
}

void exception_undefined_instruction(uint32_t *regs)
{
	printk(BIOS_ERR, "exception _undefined_instruction\n");
	print_regs(regs);
	die("exception");
}

void exception_software_interrupt(uint32_t *regs)
{
	printk(BIOS_ERR, "exception _software_interrupt\n");
	print_regs(regs);
	die("exception");
}

void exception_prefetch_abort(uint32_t *regs)
{
	printk(BIOS_ERR, "exception _prefetch_abort\n");
	print_regs(regs);
	die("exception");
}

void exception_data_abort(uint32_t *regs)
{
	if (test_abort) {
		regs[15] = regs[0];
		return;
	} else {
		printk(BIOS_ERR, "exception _data_abort\n");
		print_regs(regs);
	}
	die("exception");
}

void exception_not_used(uint32_t *regs)
{
	printk(BIOS_ERR, "exception _not_used\n");
	print_regs(regs);
	die("exception");
}

void exception_irq(uint32_t *regs)
{
	printk(BIOS_ERR, "exception _irq\n");
	print_regs(regs);
	die("exception");
}

void exception_fiq(uint32_t *regs)
{
	printk(BIOS_ERR, "exception _fiq\n");
	print_regs(regs);
	die("exception");
}

static inline uint32_t get_sctlr(void)
{
	uint32_t val;
	asm("mrc p15, 0, %0, c1, c0, 0" : "=r" (val));
	return val;
}

static inline void set_sctlr(uint32_t val)
{
	asm volatile("mcr p15, 0, %0, c1, c0, 0" :: "r" (val));
	asm volatile("" ::: "memory");
}

void exception_init(void)
{
	static const uint32_t sctlr_te = (0x1 << 30);
	static const uint32_t sctlr_v = (0x1 << 13);
	static const uint32_t sctlr_a = (0x1 << 1);

	uint32_t sctlr = get_sctlr();
	/* Handle exceptions in ARM mode. */
	sctlr &= ~sctlr_te;
	/* Set V=0 in SCTLR so VBAR points to the exception vector table. */
	sctlr &= ~sctlr_v;
	/* Enforce alignment temporarily. */
	set_sctlr(sctlr | sctlr_a);

	extern uint32_t exception_table[];
	set_vbar((uintptr_t)exception_table);

	test_abort = 1;
	printk(BIOS_ERR, "Testing exceptions\n");
	exception_test();
	test_abort = 0;
	printk(BIOS_ERR, "Testing exceptions: DONE\n");

	/* Restore original alignment settings. */
	set_sctlr(sctlr);
}