blob: 0da7f1528e3720895f77236149547f51d2f65134 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
|
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */
#include <device/device.h>
#include <cpu/cpu.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/lapic.h>
#include <cpu/intel/microcode.h>
#include <cpu/intel/hyperthreading.h>
#include <cpu/intel/common/common.h>
#include <cpu/x86/cache.h>
static void model_f3x_init(struct device *cpu)
{
/* Turn on caching if we haven't already */
x86_enable_cache();
if (!CONFIG(PARALLEL_MP) && !intel_ht_sibling()) {
/* MTRRs are shared between threads */
x86_setup_mtrrs();
x86_mtrr_check();
/* Update the microcode */
intel_update_microcode_from_cbfs();
}
/* Enable the local CPU APICs */
setup_lapic();
/* Start up my CPU siblings */
if (!CONFIG(PARALLEL_MP))
intel_sibling_init(cpu);
};
static struct device_operations cpu_dev_ops = {
.init = model_f3x_init,
};
static const struct cpu_device_id cpu_table[] = {
{ X86_VENDOR_INTEL, 0x0f34 }, /* Xeon */
{ 0, 0 },
};
static const struct cpu_driver model_f3x __cpu_driver = {
.ops = &cpu_dev_ops,
.id_table = cpu_table,
};
|
