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chip soc/intel/meteorlake
# GPE configuration
register "pmc_gpe0_dw0" = "GPP_B"
register "pmc_gpe0_dw1" = "GPP_E"
register "pmc_gpe0_dw2" = "GPP_F"
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x000c0201"
# EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901"
register "usb2_ports[0]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 0
register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 1
register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 2
register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 3
register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 4
register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 5
register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 6
register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 7
register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 8
register "usb2_ports[9]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 9
register "usb3_ports[0]" = "USB3_PORT_EMPTY" # Disable USB3.0 Port 0
register "usb3_ports[1]" = "USB3_PORT_EMPTY" # Disable USB3.0 Port 1
register "tcss_ports[0]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 0
register "tcss_ports[1]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 1
register "tcss_ports[2]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 2
register "tcss_ports[3]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 3
# S0ix enable
register "s0ix_enable" = "1"
# Disable C1 C-state auto-demotion
register "disable_c1_state_auto_demotion" = "1"
# Disable PKGC-state demotion
register "disable_package_c_state_demotion" = "1"
# Enable Energy Reporting
register "pch_pm_energy_report_enable" = "1"
# DPTF enable
register "dptf_enable" = "1"
# Enable CNVi BT
register "cnvi_bt_core" = "true"
register "sagv" = "SAGV_ENABLED"
register "sagv_freq_mhz[0]" = "2133"
register "sagv_gear[0]" = "4"
register "sagv_freq_mhz[1]" = "4267"
register "sagv_gear[1]" = "4"
register "sagv_freq_mhz[2]" = "6000"
register "sagv_gear[2]" = "4"
register "sagv_freq_mhz[3]" = "6400"
register "sagv_gear[3]" = "4"
# Set on-board graphics as primary display
register "skip_ext_gfx_scan" = "1"
register "serial_io_uart_mode" = "{
[PchSerialIoIndexUART0] = PchSerialIoPci,
[PchSerialIoIndexUART1] = PchSerialIoDisabled,
[PchSerialIoIndexUART2] = PchSerialIoDisabled,
}"
register "pch_hda_dsp_enable" = "1"
register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
register "pch_hda_idisp_codec_enable" = "1"
# As per doc 640982, Intel MTL-U 15W CPU supports FVM on IA and SA
# The ICC Limit is represented in 1/4 A increments, i.e., a value of 400 = 100A
# For IA VR configuration
register "enable_fast_vmode[VR_DOMAIN_IA]" = "1"
register "cep_enable[VR_DOMAIN_IA]" = "1"
register "fast_vmode_i_trip[VR_DOMAIN_IA]" = "264" # 66A
# For SA VR configuration
register "enable_fast_vmode[VR_DOMAIN_SA]" = "1"
register "cep_enable[VR_DOMAIN_SA]" = "1"
register "fast_vmode_i_trip[VR_DOMAIN_SA]" = "84" # 21A
device domain 0 on
device ref igpu on end
device ref dtt on end
device ref ioe_shared_sram on end
device ref xhci on end
device ref pmc_shared_sram on end
device ref heci1 on end
device ref uart0 on end
device ref soc_espi on
chip ec/google/chromeec
device pnp 0c09.0 on end
end
end
end
end
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