blob: 0e8d321f85610088b3f3924add708920c83d43b7 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
|
FLASH 32M {
SI_ALL 6M {
SI_DESC 4K
SI_EC 512K
SI_ME {
CSE_LAYOUT 8K
CSE_RO 1588K
CSE_DATA 512K
# 64-KiB aligned to optimize RW erases during CSE update.
CSE_RW 3520K
}
}
SI_BIOS 26M {
RW_SECTION_A 8M {
VBLOCK_A 64K
FW_MAIN_A(CBFS)
RW_FWID_A 64
}
RW_LEGACY(CBFS) 1M
RW_MISC 1M {
UNIFIED_MRC_CACHE(PRESERVE) 192K {
RECOVERY_MRC_CACHE 64K
RW_MRC_CACHE 128K
}
RW_ELOG(PRESERVE) 16K
RW_SHARED 16K {
SHARED_DATA 8K
VBLOCK_DEV 8K
}
RW_VPD(PRESERVE) 8K
RW_NVRAM(PRESERVE) 24K
}
# This section starts at the 16M boundary in SPI flash.
# ADL does not support a region crossing this boundary,
# because the SPI flash is memory-mapped into two non-
# contiguous windows.
RW_SECTION_B 8M {
VBLOCK_B 64K
FW_MAIN_B(CBFS)
RW_FWID_B 64
}
# Make WP_RO region align with SPI vendor
# memory protected range specification.
WP_RO 8M {
RO_VPD(PRESERVE) 16K
RO_SECTION {
FMAP 2K
RO_FRID 64
GBB@4K 448K
COREBOOT(CBFS)
}
}
}
}
|
