src/mainboard/intel/adlrvp/memory_rpl.c


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

/* SPDX-License-Identifier: GPL-2.0-only */

#include <baseboard/variants.h>
#include <soc/romstage.h>

#include "board_id.h"

void rpl_memory_params(FSPM_UPD *memupd)
{
	FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig;

	int board_id = get_board_id();

	switch (board_id) {
	case ADL_P_LP4_1:
	case ADL_P_LP4_2:
	case ADL_P_DDR4_1:
	case ADL_P_DDR4_2:
	case ADL_P_DDR5_1:
	case ADL_P_DDR5_2:
	default:
		return;
	case ADL_P_LP5_1:
	case ADL_P_LP5_2:
		mem_cfg->Lp5BankMode = 1;
		return;
	}
}