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##
## This file is part of the coreboot project.
##
## Copyright (C) 2015-2018 Intel Corp.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
if BOARD_INTEL_GALILEO
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_8192
select ENABLE_BUILTIN_HSUART1
select HAVE_ACPI_TABLES
select SOC_INTEL_QUARK
select MAINBOARD_HAS_I2C_TPM_ATMEL
select MAINBOARD_HAS_TPM2
select UDK_2015_BINDING
config MAINBOARD_DIR
string
default intel/galileo
config MAINBOARD_PART_NUMBER
string
default "Galileo"
config MAINBOARD_VENDOR
string
default "Intel"
config GALILEO_GEN2
bool "Board generation: GEN1 (n) or GEN2 (y)"
default y
help
The coreboot binary will configure only one generation of the Galileo
board since coreboot can not determine the board generation at
runtime. Select which generation of the Galileo that coreboot
should initialize.
choice
prompt "FSP binary type"
default FSP_BUILD_TYPE_DEBUG
config FSP_BUILD_TYPE_DEBUG
bool "Debug"
help
Use the debug version of FSP
config FSP_BUILD_TYPE_RELEASE
bool "Release"
help
Use the release version of FSP
endchoice
config FSP_BUILD_TYPE
string
default "DEBUG" if FSP_BUILD_TYPE_DEBUG
default "RELEASE" if FSP_BUILD_TYPE_RELEASE
choice
prompt "FSP type"
default FSP_TYPE_2_0_PEI
config FSP_TYPE_2_0
bool "MemInit subroutine"
help
FSP 2.0 implemented as subroutines, no EDK-II cores
config FSP_TYPE_2_0_PEI
bool "SEC + PEI Core + MemInit PEIM"
help
FSP 2.0 implemented using SEC and PEI core
endchoice
config FSP_TYPE
string
default "Fsp2_0" if FSP_TYPE_2_0
default "Fsp2_0Pei" if FSP_TYPE_2_0_PEI
config FSP_DEBUG_ALL
bool "Enable all FSP debug support"
default y
# Enable display and verification for coreboot build tests
select DISPLAY_HOBS
select DISPLAY_MTRRS
select DISPLAY_UPD_DATA
select DISPLAY_ESRAM_LAYOUT
select DISPLAY_FSP_CALLS_AND_STATUS
select DISPLAY_FSP_HEADER
select VERIFY_HOBS
help
Turn on debug support to display HOBS, MTRRS, SMM_MEMORY_MAP, UPD_DATA
also turn on FSP 2.0 debug support for ESRAM_LAYOUT,
FSP_CALLS_AND_STATUS, FSP_HEADER, POSTCAR_CONSOLE and VERIFY_HOBS
config VBOOT_WITH_CRYPTO_SHIELD
bool "Verified boot using the Crypto Shield board"
default n
select COLLECT_TIMESTAMPS
select VBOOT_SEPARATE_VERSTAGE
select VBOOT
select VBOOT_STARTS_IN_BOOTBLOCK
select VBOOT_SOFT_REBOOT_WORKAROUND
select VBOOT_VBNV_CMOS
help
Perform a verified boot using the TPM on the Crypto Shield board.
config DRIVER_TPM_I2C_ADDR
hex "Address of the I2C TPM chip"
depends on VBOOT_WITH_CRYPTO_SHIELD
default 0x29
help
I2C address of the TPM chip on the Crypto Shield board.
config FMDFILE
string "FMAP description file in fmd format"
depends on VBOOT
default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot.fmd"
help
The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE,
but in some cases more complex setups are required.
When an FMD descriptionn file is specified, the build system uses it
instead of creating a default FMAP file.
config ENABLE_SD_TESTING
bool "Enable SD card testing"
default y
select COMMONLIB_STORAGE_SD
select SDHC_DEBUG
select STORAGE_LOG
select STORAGE_TEST
endif # BOARD_INTEL_QUARK
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