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|
fw_config
field AUDIO 8 10
option NONE 0
option MTL_ALC1019_ALC5682I_I2S 1
option MTL_MAX98373_ALC5682_SNDW 2
option MTL_ALC711_SNDW 3
option MTL_ALC5682I_MAX9857A_I2S 4
end
end
chip soc/intel/meteorlake
# GPE configuration
register "pmc_gpe0_dw0" = "GPP_B"
register "pmc_gpe0_dw1" = "GPP_D"
register "pmc_gpe0_dw2" = "GPP_E"
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x000c0201"
# EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901"
register "serial_io_uart_mode" = "{
[PchSerialIoIndexUART0] = PchSerialIoPci,
[PchSerialIoIndexUART1] = PchSerialIoDisabled,
[PchSerialIoIndexUART2] = PchSerialIoDisabled,
}"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C0
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C1
register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C2
register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C3
register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-A Port A0
register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # Type-A Port A1
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # FPS connector
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN / MCF
register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # MCF / M.2 WWAN
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WLAN
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2_Type-A1 / M.2 WWAN
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2_Type-A0 / USB Flex Connector
register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC0)"
register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC0)"
register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC0)"
register "tcss_ports[3]" = "TCSS_PORT_DEFAULT(OC0)"
# Enable CNVi BT
register "cnvi_bt_core" = "true"
# Enable S0ix
register "s0ix_enable" = "1"
# Enable EDP in PortA
register "ddi_port_A_config" = "1"
# Enable HDMI in Port B
register "ddi_ports_config" = "{
[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
}"
register "serial_io_i2c_mode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C1] = PchSerialIoPci,
[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
[PchSerialIoIndexI2C3] = PchSerialIoPci,
[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
}"
# Intel Common SoC Config
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.i2c[0] = {
.speed = I2C_SPEED_FAST,
},
.i2c[1] = {
.speed = I2C_SPEED_FAST,
},
.i2c[3] = {
.speed = I2C_SPEED_FAST,
},
}"
register "serial_io_gspi_mode" = "{
[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
[PchSerialIoIndexGSPI1] = PchSerialIoPci,
}"
register "serial_io_gspi_cs_mode" = "{
[PchSerialIoIndexGSPI0] = 0,
[PchSerialIoIndexGSPI1] = 0,
}"
register "serial_io_gspi_cs_state" = "{
[PchSerialIoIndexGSPI0] = 0,
[PchSerialIoIndexGSPI1] = 0,
}"
# HD Audio
register "pch_hda_dsp_enable" = "1"
register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
register "pch_hda_idisp_codec_enable" = "1"
# DPTF enable
register "dptf_enable" = "1"
device domain 0 on
device ref igpu on end
device ref dtt on
chip drivers/intel/dptf
## sensor information
register "options.tsr[0].desc" = ""Ambient""
register "options.tsr[1].desc" = ""DDR""
register "options.tsr[2].desc" = ""Skin""
register "options.tsr[3].desc" = ""Battery""
## Active Policy
# TODO: below values are initial reference values only
register "policies.active" = "{
[0] = {
.target = DPTF_CPU,
.thresholds = {
TEMP_PCT(95, 90),
TEMP_PCT(90, 80),
}
},
[1] = {
.target = DPTF_TEMP_SENSOR_0,
.thresholds = {
TEMP_PCT(80, 90),
TEMP_PCT(70, 80),
}
}
}"
## Passive Policy
# TODO: below values are initial reference values only
register "policies.passive" = "{
[0] = DPTF_PASSIVE(CPU, CPU, 95, 10000),
[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 50000),
[2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 85, 50000),
[3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 85, 50000),
[4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 85, 50000),
}"
## Critical Policy
# TODO: below values are initial reference values only
register "policies.critical" = "{
[0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 95, SHUTDOWN),
[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 95, SHUTDOWN),
[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 95, SHUTDOWN),
[4] = DPTF_CRITICAL(TEMP_SENSOR_3, 95, SHUTDOWN),
}"
## Power Limits Control
register "controls.power_limits" = "{
.pl1 = {
.min_power = 35000,
.max_power = 45000,
.time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 32 * MSECS_PER_SEC,
.granularity = 200,
},
.pl2 = {
.min_power = 56000,
.max_power = 56000,
.time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 32 * MSECS_PER_SEC,
.granularity = 1000,
}
}"
## Charger Performance Control (Control, mA)
register "controls.charger_perf" = "{
[0] = { 255, 3000 },
[1] = { 24, 1500 },
[2] = { 16, 1000 },
[3] = { 8, 500 }
}"
## Fan Performance Control (Percent, Speed, Noise, Power)
register "controls.fan_perf" = "{
[0] = { 90, 6700, 220, 2200, },
[1] = { 80, 5800, 180, 1800, },
[2] = { 70, 5000, 145, 1450, },
[3] = { 60, 4900, 115, 1150, },
[4] = { 50, 3838, 90, 900, },
[5] = { 40, 2904, 55, 550, },
[6] = { 30, 2337, 30, 300, },
[7] = { 20, 1608, 15, 150, },
[8] = { 10, 800, 10, 100, },
[9] = { 0, 0, 0, 50, }
}"
## Fan options
register "options.fan.fine_grained_control" = "1"
register "options.fan.step_size" = "2"
device generic 0 alias dptf_policy on end
end
end
device ref heci1 on end
device ref tbt_pcie_rp0 on end
device ref tbt_pcie_rp1 on end
device ref tbt_pcie_rp2 on end
device ref tbt_pcie_rp3 on end
device ref tcss_xhci on
chip drivers/usb/acpi
device ref tcss_root_hub on
chip drivers/usb/acpi
register "desc" = ""USB3 Type-C Port C0""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "group" = "ACPI_PLD_GROUP(4, 2)"
device ref tcss_usb3_port1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-C Port C1""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "group" = "ACPI_PLD_GROUP(3, 2)"
device ref tcss_usb3_port2 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-C Port C2""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "group" = "ACPI_PLD_GROUP(2, 2)"
device ref tcss_usb3_port3 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-C Port C3""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "group" = "ACPI_PLD_GROUP(1, 2)"
device ref tcss_usb3_port4 on end
end
end
end
end
device ref tcss_dma0 on
chip drivers/intel/usb4/retimer
register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
use tcss_usb3_port1 as dfp[0].typec_port
device generic 0 on end
end
chip drivers/intel/usb4/retimer
register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
use tcss_usb3_port2 as dfp[1].typec_port
device generic 0 on end
end
end
device ref tcss_dma1 on
chip drivers/intel/usb4/retimer
register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
use tcss_usb3_port3 as dfp[0].typec_port
device generic 0 on end
end
chip drivers/intel/usb4/retimer
register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
use tcss_usb3_port4 as dfp[1].typec_port
device generic 0 on end
end
end
device ref pcie_rp7 on
# Enable PCH PCIE RP 7 using CLK 1
register "pcie_rp[PCIE_RP(7)]" = "{
.clk_src = 1,
.clk_req = 1,
.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
}"
chip soc/intel/common/block/pcie/rtd3
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C05)"
register "reset_off_delay_ms" = "20"
register "srcclk_pin" = "1"
register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
register "skip_on_off_support" = "true"
device generic 0 alias rp7_rtd3 on end
end
chip drivers/wwan/fm
register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E07)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A15)"
register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C05)"
register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F10)"
register "add_acpi_dma_property" = "true"
use rp7_rtd3 as rtd3dev
device generic 0 on end
end
end # WWAN
device ref pcie_rp8 on
# Enable PCH PCIE RP 8 using CLK 5
register "pcie_rp[PCIE_RP(8)]" = "{
.clk_src = 5,
.clk_req = 5,
.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
}"
end # WLAN
device ref pcie_rp10 on
# Enable SSD Gen4 PCIE 10 using CLK 8
register "pcie_rp[PCIE_RP(10)]" = "{
.clk_src = 8,
.clk_req = 8,
.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
}"
end # PCIE10 SSD Gen4
device ref pcie_rp11 on
# Enable SSD Gen4 PCIE 11 using CLK 7
register "pcie_rp[PCIE_RP(11)]" = "{
.clk_src = 7,
.clk_req = 7,
.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
}"
end # PCIE11 SSD Gen4
device ref xhci on
chip drivers/usb/acpi
device ref xhci_root_hub on
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Port 1""
register "type" = "UPC_TYPE_A"
register "group" = "ACPI_PLD_GROUP(1, 1)"
device ref usb2_port1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Port 2""
register "type" = "UPC_TYPE_A"
register "group" = "ACPI_PLD_GROUP(2, 1)"
device ref usb2_port2 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Port 3""
register "type" = "UPC_TYPE_A"
register "group" = "ACPI_PLD_GROUP(3, 1)"
device ref usb2_port3 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Port 4""
register "type" = "UPC_TYPE_A"
register "group" = "ACPI_PLD_GROUP(4, 1)"
device ref usb2_port4 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Port 5""
register "type" = "UPC_TYPE_A"
register "group" = "ACPI_PLD_GROUP(5, 1)"
device ref usb2_port5 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Port 6""
register "type" = "UPC_TYPE_A"
register "group" = "ACPI_PLD_GROUP(6, 1)"
device ref usb2_port6 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Port 7""
register "type" = "UPC_TYPE_A"
register "group" = "ACPI_PLD_GROUP(7, 1)"
device ref usb2_port7 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Port 8""
register "type" = "UPC_TYPE_A"
register "group" = "ACPI_PLD_GROUP(8, 1)"
device ref usb2_port8 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Port 9""
register "type" = "UPC_TYPE_A"
register "group" = "ACPI_PLD_GROUP(9, 1)"
device ref usb2_port9 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Port 10""
register "type" = "UPC_TYPE_A"
register "group" = "ACPI_PLD_GROUP(10, 1)"
device ref usb2_port10 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-A Port 1""
register "type" = "UPC_TYPE_USB3_A"
register "group" = "ACPI_PLD_GROUP(1, 2)"
device ref usb3_port1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-A Port 2""
register "type" = "UPC_TYPE_USB3_A"
register "group" = "ACPI_PLD_GROUP(2, 2)"
device ref usb3_port2 on end
end
end
end
end
device ref cnvi_wifi on
chip drivers/wifi/generic
register "wake" = "GPE0_PME_B0"
register "enable_cnvi_ddr_rfim" = "true"
device generic 0 on end
end
end
device ref i2c0 on end
device ref i2c1 on end
device ref i2c2 on end
device ref i2c3 on
chip drivers/i2c/generic
register "hid" = ""10EC5682""
register "name" = ""RT58""
register "desc" = ""Headset Codec""
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_S05)"
register "probed" = "1"
# jd_src RT5668_JD1 = 1, RT5682_JD_NULL = 0
register "property_count" = "1"
register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
register "property_list[0].name" = ""realtek,jd-src""
register "property_list[0].integer" = "1"
device i2c 1a on
probe AUDIO MTL_ALC1019_ALC5682I_I2S
probe AUDIO MTL_ALC5682I_MAX9857A_I2S
end
end
# Ref config #5 for Chrome, transducer card config 5A
#+-------------------+-------------------+
#| Speaker Amp | Assignment |
#+-------------------+-------------------+
#| SPK 0 | left |
#| SPK 1 | right |
#| SPK 2 | top left |
#| SPK 3 | top right |
#+-------------------+-------------------+
chip drivers/i2c/generic
register "hid" = ""10EC1019""
register "desc" = ""Realtek SPK AMP L""
register "uid" = "0"
device i2c 28 on
probe AUDIO MTL_ALC1019_ALC5682I_I2S
end
end
chip drivers/i2c/generic
register "hid" = ""10EC1019""
register "desc" = ""Realtek SPK AMP R""
register "uid" = "1"
device i2c 29 on
probe AUDIO MTL_ALC1019_ALC5682I_I2S
end
end
chip drivers/i2c/generic
register "hid" = ""10EC1019""
register "desc" = ""Realtek SPK AMP TL""
register "uid" = "2"
device i2c 2a on
probe AUDIO MTL_ALC1019_ALC5682I_I2S
end
end
chip drivers/i2c/generic
register "hid" = ""10EC1019""
register "desc" = ""Realtek SPK AMP TR""
register "uid" = "3"
device i2c 2b on
probe AUDIO MTL_ALC1019_ALC5682I_I2S
end
end
end # I2C3
device ref i2c4 on end
device ref i2c5 on end
device ref shared_sram on end
device ref uart0 on end
device ref gspi1 on end
device ref smbus on end
device ref hda on
chip drivers/intel/soundwire
device generic 0 on
chip drivers/soundwire/alc711
# SoundWire Link 0 ID 1
register "desc" = ""Headset Codec""
device generic 0.1 on
probe AUDIO MTL_ALC711_SNDW
end
end
chip drivers/soundwire/alc5682
# SoundWire Link 2 ID 1
register "desc" = ""Headset Codec""
device generic 2.1 on
probe AUDIO MTL_MAX98373_ALC5682_SNDW
end
end
chip drivers/soundwire/max98373
# SoundWire Link 0 ID 3
register "desc" = ""Left Speaker Amp""
device generic 0.3 on
probe AUDIO MTL_MAX98373_ALC5682_SNDW
end
end
chip drivers/soundwire/max98373
# SoundWire Link 0 ID 7
register "desc" = ""Right Speaker Amp""
device generic 0.7 on
probe AUDIO MTL_MAX98373_ALC5682_SNDW
end
end
chip drivers/generic/max98357a
register "hid" = ""MX98357A""
register "sdmode_gpio" =
"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_S04)"
register "sdmode_delay" = "5"
device generic 0 on
probe AUDIO MTL_ALC5682I_MAX9857A_I2S
end
end
end
end
end
end
end
|
