1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
|
chip soc/intel/tigerlake
# GPE configuration
# Note that GPE events called out in ASL code rely on this
# route. i.e. If this route changes then the affected GPE
# offset bits also need to be changed.
register "pmc_gpe0_dw0" = "GPP_B"
register "pmc_gpe0_dw1" = "GPP_C"
register "pmc_gpe0_dw2" = "GPP_D"
# FSP configuration
register "SaGv" = "SaGv_Disabled"
# CNVi BT enable/disable
register "CnviBtCore" = "true"
register "usb2_ports[0]" = "USB2_PORT_MID(OC3)" # Type-C Port1
register "usb2_ports[1]" = "USB2_PORT_EMPTY" # M.2 WWAN
register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # M.2 Bluetooth, USB3/2 Type A Port1
register "usb2_ports[3]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A Port 1
register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-C Port2
register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-C Port3 / MECC
register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Not used
register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Not used
register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Not used
register "usb2_ports[9]" = "USB2_PORT_MID(OC3)" # CNVi/BT
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port1
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # USB3/USB2 Flex Connector
# CPU replacement check
register "CpuReplacementCheck" = "1"
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x000c0201"
# EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901"
register "PcieRpEnable[2]" = "1"
register "PcieRpEnable[3]" = "1"
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[10]" = "1"
register "PcieRpSlotImplemented[2]" = "1"
register "PcieRpSlotImplemented[3]" = "1"
register "PcieRpSlotImplemented[8]" = "1"
register "PcieRpSlotImplemented[10]" = "1"
# Enable PR LTR
register "PcieRpLtrEnable[2]" = "1"
register "PcieRpLtrEnable[3]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpLtrEnable[10]" = "1"
# Hybrid storage mode
register "HybridStorageMode" = "1"
register "PcieClkSrcClkReq[1]" = "1"
register "PcieClkSrcClkReq[2]" = "2"
register "PcieClkSrcClkReq[3]" = "3"
register "PcieClkSrcUsage[1]" = "0x2"
register "PcieClkSrcUsage[2]" = "0x3"
register "PcieClkSrcUsage[3]" = "0x8"
# enabling EDP in PortA
register "DdiPortAConfig" = "1"
register "DdiPortAHpd" = "1"
register "DdiPortADdc" = "0"
register "DdiPortBHpd" = "1"
register "DdiPortBDdc" = "1"
register "DdiPortCHpd" = "0"
register "DdiPortCDdc" = "0"
register "DdiPort1Hpd" = "1"
register "DdiPort1Ddc" = "0"
register "DdiPort2Hpd" = "1"
register "DdiPort2Ddc" = "0"
register "SerialIoI2cMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C1] = PchSerialIoPci,
[PchSerialIoIndexI2C2] = PchSerialIoPci,
[PchSerialIoIndexI2C3] = PchSerialIoPci,
[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
[PchSerialIoIndexI2C5] = PchSerialIoPci,
}"
register "SerialIoGSpiMode" = "{
[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
[PchSerialIoIndexGSPI1] = PchSerialIoPci,
[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
[PchSerialIoIndexGSPI3] = PchSerialIoDisabled,
}"
register "SerialIoGSpiCsMode" = "{
[PchSerialIoIndexGSPI0] = 0,
[PchSerialIoIndexGSPI1] = 1,
[PchSerialIoIndexGSPI2] = 0,
[PchSerialIoIndexGSPI3] = 0,
}"
register "SerialIoGSpiCsState" = "{
[PchSerialIoIndexGSPI0] = 0,
[PchSerialIoIndexGSPI1] = 0,
[PchSerialIoIndexGSPI2] = 0,
[PchSerialIoIndexGSPI3] = 0,
}"
register "SerialIoUartMode" = "{
[PchSerialIoIndexUART0] = PchSerialIoDisabled,
[PchSerialIoIndexUART1] = PchSerialIoDisabled,
[PchSerialIoIndexUART2] = PchSerialIoPci,
}"
# TCSS USB3
register "TcssXhciEn" = "1"
register "TcssAuxOri" = "0"
# Enable S0ix
register "s0ix_enable" = "1"
# Enable DPTF
register "dptf_enable" = "1"
# Add PL1 and PL2 values
register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{
.tdp_pl1_override = 9,
.tdp_pl2_override = 35,
.tdp_pl4 = 66,
}"
register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{
.tdp_pl1_override = 9,
.tdp_pl2_override = 40,
.tdp_pl4 = 83,
}"
#HD Audio
register "PchHdaDspEnable" = "1"
register "PchHdaAudioLinkHdaEnable" = "0"
register "PchHdaAudioLinkDmicEnable[0]" = "1"
register "PchHdaAudioLinkDmicEnable[1]" = "1"
register "PchHdaAudioLinkSspEnable[0]" = "1"
register "PchHdaAudioLinkSspEnable[1]" = "0"
register "PchHdaAudioLinkSspEnable[2]" = "1"
register "PchHdaAudioLinkSndwEnable[0]" = "1"
# Intel Common SoC Config
register "common_soc_config" = "{
.gspi[1] = {
.speed_mhz = 1,
.early_init = 1,
},
.i2c[0] = {
.speed = I2C_SPEED_FAST,
},
.i2c[1] = {
.speed = I2C_SPEED_FAST,
},
.i2c[2] = {
.speed = I2C_SPEED_FAST,
},
.i2c[3] = {
.speed = I2C_SPEED_FAST,
},
.i2c[5] = {
.speed = I2C_SPEED_FAST,
},
}"
device domain 0 on
#From EDS(575683)
device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y
device pci 02.0 on end # Graphics
device pci 04.0 on
# Default DPTF Policy for all tglrvp_up4 boards if not overridden
chip drivers/intel/dptf
register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 1000)"
register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 105, SHUTDOWN)"
# Power Limits Control
register "controls.power_limits.pl1" = "{
.min_power = 3000,
.max_power = 9000,
.time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 32 * MSECS_PER_SEC,
.granularity = 200,}"
register "controls.power_limits.pl2" = "{
.min_power = 40000,
.max_power = 40000,
.time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 32 * MSECS_PER_SEC,
.granularity = 1000,}"
device generic 0 on end
end
end # DPTF 0x9A02:Y22/0x9A12:Y42
device pci 05.0 on end # IPU 0x9A19
device pci 06.0 on end # PEG60 0x9A09
device pci 07.0 on end # TBT_PCIe0 0x9A23
device pci 07.1 on end # TBT_PCIe1 0x9A25
device pci 07.2 on end # TBT_PCIe2 0x9A27
device pci 07.3 off end # TBT_PCIe3 0x9A29
device pci 08.0 off end # GNA 0x9A11
device pci 09.0 off end # NPK 0x9A33
device pci 0a.0 off end # Crash-log SRAM 0x9A0D
device pci 0d.0 on end # USB xHCI 0x9A13
device pci 0d.1 on end # USB xDCI (OTG) 0x9A15
device pci 0d.2 on end # TBT DMA0 0x9A1B
device pci 0d.3 on end # TBT DMA1 0x9A1D
device pci 0e.0 off end # VMD 0x9A0B
# From PCH EDS(576591)
device pci 10.6 off end # THC0 0xA0D0
device pci 10.7 off end # THC1 0xA0D1
device pci 12.0 on # SensorHUB 0xA0FC
chip drivers/intel/ish
register "firmware_name" = ""tglrvp_ish.bin""
device generic 0 on end
end
end
device pci 12.6 off end # GSPI2 0x34FB
device pci 13.0 off end # GSPI3 0xA0FD
device pci 14.0 on end # USB3.1 xHCI 0xA0ED
device pci 14.1 on end # USB3.1 xDCI 0xA0EE
device pci 14.2 on end # Shared RAM 0xA0EF
device pci 14.3 on
chip drivers/wifi/generic
register "wake" = "GPE0_PME_B0"
device generic 0 on end
end
end # CNVi: WiFi 0xA0F0 - A0F3
device pci 15.0 on # I2C0 0xA0E8
chip drivers/i2c/generic
register "hid" = ""10EC1308""
register "name" = ""RTAM""
register "desc" = ""Realtek RT1308 Codec""
device i2c 10 on end
end
chip drivers/i2c/max98373
register "vmon_slot_no" = "4"
register "imon_slot_no" = "5"
register "uid" = "0"
register "desc" = ""RIGHT SPEAKER AMP""
register "name" = ""MAXR""
device i2c 31 on end
end
chip drivers/i2c/max98373
register "vmon_slot_no" = "6"
register "imon_slot_no" = "7"
register "uid" = "1"
register "desc" = ""LEFT SPEAKER AMP""
register "name" = ""MAXL""
device i2c 32 on end
end
chip drivers/i2c/generic
register "hid" = ""10EC5682""
register "name" = ""RT58""
register "desc" = ""Realtek RT5682""
register "irq" = "ACPI_IRQ_EDGE_HIGH(GPP_C12_IRQ)"
register "probed" = "1"
# Set the jd_src to RT5668_JD1 for jack detection
register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
register "property_list[0].name" = ""realtek,jd-src""
register "property_list[0].integer" = "1"
device i2c 1a on end
end
end # I2C0
device pci 15.1 on end # I2C1 0xA0E9
device pci 15.2 on end # I2C2 0xA0EA
device pci 15.3 on end # I2C3 0xA0EB
device pci 16.0 on end # HECI1 0xA0E0
device pci 16.1 off end # HECI2 0xA0E1
device pci 16.2 off end # CSME 0xA0E2
device pci 16.3 off end # CSME 0xA0E3
device pci 16.4 off end # HECI3 0xA0E4
device pci 16.5 off end # HECI4 0xA0E5
device pci 17.0 on end # SATA 0xA0D3
device pci 19.0 off end # I2C4 0xA0C5
device pci 19.1 on end # I2C5 0xA0C6
device pci 19.2 on end # UART2 0xA0C7
device pci 1c.0 off end # RP1 0xA0B8
device pci 1c.1 off end # RP2 0xA0B9
device pci 1c.2 on end # RP3 0xA0BA
device pci 1c.3 on
chip soc/intel/common/block/pcie/rtd3
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B17)"
register "srcclk_pin" = "2"
device generic 0 on end
end
end # RP4 0xA0BB
device pci 1c.4 off end # RP5 0xA0BC
device pci 1c.5 off end # RP6 0xA0BD
device pci 1c.6 off end # RP7 0xA0BE
device pci 1c.7 off end # RP8 0xA0BF
device pci 1d.0 on end # RP9 0xA0B0
device pci 1d.1 off end # RP10 0xA0B1
device pci 1d.2 on end # RP11 0xA0B2
device pci 1d.3 off end # RP12 0xA0B3
device pci 1e.0 off end # UART0 0xA0A8
device pci 1e.1 off end # UART1 0xA0A9
device pci 1e.2 on end # GSPI0 0xA0AA
device pci 1e.3 on
chip drivers/spi/acpi
register "hid" = "ACPI_DT_NAMESPACE_HID"
register "compat_string" = ""google,cr50""
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C22_IRQ)"
device spi 0 on end
end
end # GSPI1 0xA0AB
device pci 1f.0 on
chip ec/google/chromeec
use conn0 as mux_conn[0]
use conn1 as mux_conn[1]
device pnp 0c09.0 on end
end
end # eSPI 0xA080 - A09F
device pci 1f.1 on end # P2SB 0xA0A0
device pci 1f.2 hidden # PMC 0xA0A1
# The pmc_mux chip driver is a placeholder for the
# PMC.MUX device in the ACPI hierarchy.
chip drivers/intel/pmc_mux
device generic 0 on
chip drivers/intel/pmc_mux/conn
use usb2_port6 as usb2_port
use tcss_usb3_port3 as usb3_port
# SBU is fixed, HSL follows CC
register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
device generic 0 alias conn0 on end
end
chip drivers/intel/pmc_mux/conn
use usb2_port5 as usb2_port
use tcss_usb3_port2 as usb3_port
# SBU is fixed, HSL follows CC
register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
device generic 1 alias conn1 on end
end
end
end
end # PMC
device pci 1f.3 on end # Intel HD audio 0xA0C8-A0CF
device pci 1f.4 on end # SMBus 0xA0A3
device pci 1f.5 on end # SPI 0xA0A4
device pci 1f.6 off end # GbE 0x15E1/0x15E2
device pci 1f.7 off end # TH 0xA0A6
end
end
|
