1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
|
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <arch/io.h>
#include <stdint.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <stdlib.h>
#include <string.h>
#include <cbmem.h>
#include <cpu/cpu.h>
#include <arch/acpi.h>
#include "i945.h"
static int get_pcie_bar(u32 *base)
{
device_t dev;
u32 pciexbar_reg;
*base = 0;
dev = dev_find_slot(0, PCI_DEVFN(0, 0));
if (!dev)
return 0;
pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
if (!(pciexbar_reg & (1 << 0)))
return 0;
switch ((pciexbar_reg >> 1) & 3) {
case 0: // 256MB
*base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28));
return 256;
case 1: // 128M
*base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
return 128;
case 2: // 64M
*base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26));
return 64;
}
return 0;
}
static void pci_domain_set_resources(device_t dev)
{
uint32_t pci_tolm;
uint8_t tolud, reg8;
uint16_t reg16;
unsigned long long tomk, tomk_stolen;
uint64_t uma_memory_base = 0, uma_memory_size = 0;
uint64_t tseg_memory_base = 0, tseg_memory_size = 0;
/* Can we find out how much memory we can use at most
* this way?
*/
pci_tolm = find_pci_tolm(dev->link_list);
printk(BIOS_DEBUG, "pci_tolm: 0x%x\n", pci_tolm);
printk(BIOS_SPEW, "Base of stolen memory: 0x%08x\n",
pci_read_config32(dev_find_slot(0, PCI_DEVFN(2, 0)), BSM));
tolud = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), TOLUD);
printk(BIOS_SPEW, "Top of Low Used DRAM: 0x%08x\n", tolud << 24);
tomk = tolud << 14;
tomk_stolen = tomk;
/* Note: subtract IGD device and TSEG */
reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC);
if (!(reg16 & 2)) {
printk(BIOS_DEBUG, "IGD decoded, subtracting ");
int uma_size = decode_igd_memory_size((reg16 >> 4) & 7);
printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10);
tomk_stolen -= uma_size;
/* For reserving UMA memory in the memory map */
uma_memory_base = tomk_stolen * 1024ULL;
uma_memory_size = uma_size * 1024ULL;
}
reg8 = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), 0x9e);
if (reg8 & 1) {
int tseg_size = 0;
printk(BIOS_DEBUG, "TSEG decoded, subtracting ");
reg8 >>= 1;
reg8 &= 3;
switch (reg8) {
case 0:
tseg_size = 1024;
break; /* TSEG = 1M */
case 1:
tseg_size = 2048;
break; /* TSEG = 2M */
case 2:
tseg_size = 8192;
break; /* TSEG = 8M */
}
printk(BIOS_DEBUG, "%dM\n", tseg_size >> 10);
tomk_stolen -= tseg_size;
/* For reserving TSEG memory in the memory map */
tseg_memory_base = tomk_stolen * 1024ULL;
tseg_memory_size = tseg_size * 1024ULL;
}
/* The following needs to be 2 lines, otherwise the second
* number is always 0
*/
printk(BIOS_INFO, "Available memory: %dK", (uint32_t)tomk_stolen);
printk(BIOS_INFO, " (%dM)\n", (uint32_t)(tomk_stolen >> 10));
/* Report the memory regions */
ram_resource(dev, 3, 0, 640);
ram_resource(dev, 4, 768, (tomk - 768));
uma_resource(dev, 5, uma_memory_base >> 10, uma_memory_size >> 10);
mmio_resource(dev, 6, tseg_memory_base >> 10, tseg_memory_size >> 10);
assign_resources(dev->link_list);
}
/* TODO We could determine how many PCIe busses we need in
* the bar. For now that number is hardcoded to a max of 64.
* See e7525/northbridge.c for an example.
*/
static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources,
.enable_resources = NULL,
.init = NULL,
.scan_bus = pci_domain_scan_bus,
.ops_pci_bus = pci_bus_default_ops,
};
static void mc_read_resources(device_t dev)
{
u32 pcie_config_base;
int buses;
pci_dev_read_resources(dev);
buses = get_pcie_bar(&pcie_config_base);
if (buses) {
struct resource *resource = new_resource(dev, PCIEXBAR);
mmconf_resource_init(resource, pcie_config_base, buses);
}
}
static void intel_set_subsystem(device_t dev, unsigned int vendor,
unsigned int device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static struct pci_operations intel_pci_ops = {
.set_subsystem = intel_set_subsystem,
};
static struct device_operations mc_ops = {
.read_resources = mc_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.acpi_fill_ssdt_generator = generate_cpu_entries,
.scan_bus = 0,
.ops_pci = &intel_pci_ops,
};
static const unsigned short pci_device_ids[] = {
0x2770, /* desktop */
0x27a0, 0x27ac, /* mobile */
0 };
static const struct pci_driver mc_driver __pci_driver = {
.ops = &mc_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.devices = pci_device_ids,
};
static void cpu_bus_init(device_t dev)
{
initialize_cpus(dev->link_list);
}
static struct device_operations cpu_bus_ops = {
.read_resources = DEVICE_NOOP,
.set_resources = DEVICE_NOOP,
.enable_resources = DEVICE_NOOP,
.init = cpu_bus_init,
.scan_bus = 0,
};
static void enable_dev(device_t dev)
{
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_DOMAIN)
dev->ops = &pci_domain_ops;
else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
dev->ops = &cpu_bus_ops;
}
struct chip_operations northbridge_intel_i945_ops = {
CHIP_NAME("Intel i945 Northbridge")
.enable_dev = enable_dev,
};
|
