1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
|
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */
#ifndef __PICASSO_SB_H__
#define __PICASSO_SB_H__
#include <types.h>
#include <device/device.h>
#include <device/pci_def.h>
#include <soc/iomap.h>
/*
* AcpiMmio Region
* - fixed addresses offset from 0xfed80000
*/
/* SMBus controller registers: 0xfed80000 or D14F0 */
#define SMB_UART_CONFIG 0xfc
#define SMB_UART3_1_8M BIT(31) /* defaults are 0 = 48MHz */
#define SMB_UART2_1_8M BIT(30)
#define SMB_UART1_1_8M BIT(29)
#define SMB_UART0_1_8M BIT(28)
#define SMB_UART_1_8M_SHIFT 28
/* Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7 */
#define PM_DECODE_EN 0x00
#define SMBUS_ASF_IO_EN BIT(4)
#define CF9_IO_EN BIT(1)
#define LEGACY_IO_EN BIT(0)
#define SMB_ASF_IO_BASE 0x01 /* part of PM_DECODE_EN in PPR */
#define PM_ISA_CONTROL 0x04
#define MMIO_EN BIT(1)
#define PM_PCI_CTRL 0x08
#define FORCE_SLPSTATE_RETRY BIT(25)
#define PWR_RESET_CFG 0x10
#define TOGGLE_ALL_PWR_GOOD BIT(1)
#define PM_SERIRQ_CONF 0x54
#define PM_SERIRQ_NUM_BITS_17 0x0000
#define PM_SERIRQ_NUM_BITS_18 0x0004
#define PM_SERIRQ_NUM_BITS_19 0x0008
#define PM_SERIRQ_NUM_BITS_20 0x000c
#define PM_SERIRQ_NUM_BITS_21 0x0010
#define PM_SERIRQ_NUM_BITS_22 0x0014
#define PM_SERIRQ_NUM_BITS_23 0x0018
#define PM_SERIRQ_NUM_BITS_24 0x001c
#define PM_SERIRQ_MODE BIT(6)
#define PM_SERIRQ_ENABLE BIT(7)
#define PM_RTC_SHADOW 0x5b /* state when power resumes */
#define PM_S5_AT_POWER_RECOVERY 0x04 /* S5 */
#define PM_RESTORE_S0_IF_PREV_S0 0x07 /* S0 if previously at S0 */
#define PM_EVT_BLK 0x60
#define WAK_STS BIT(15) /*AcpiPmEvtBlkx00 Pm1Status */
#define PCIEXPWAK_STS BIT(14)
#define RTC_STS BIT(10)
#define PWRBTN_STS BIT(8)
#define GBL_STS BIT(5)
#define BM_STS BIT(4)
#define TIMER_STS BIT(0)
#define PCIEXPWAK_DIS BIT(14) /*AcpiPmEvtBlkx02 Pm1Enable */
#define RTC_EN BIT(10)
#define PWRBTN_EN BIT(8)
#define GBL_EN BIT(5)
#define TIMER_STS BIT(0)
#define PM1_CNT_BLK 0x62
#define PM_TMR_BLK 0x64
#define PM_CPU_CTRL 0x66
#define PM_GPE0_BLK 0x68
#define PM_ACPI_SMI_CMD 0x6a
#define PM_ACPI_CONF 0x74
#define PM_ACPI_DECODE_STD BIT(0)
#define PM_ACPI_GLOBAL_EN BIT(1)
#define PM_ACPI_RTC_EN_EN BIT(2)
#define PM_ACPI_TIMER_EN_EN BIT(4)
#define PM_ACPI_MASK_ARB_DIS BIT(6)
#define PM_ACPI_BIOS_RLS BIT(7)
#define PM_ACPI_PWRBTNEN_EN BIT(8)
#define PM_ACPI_REDUCED_HW_EN BIT(9)
#define PM_ACPI_BLOCK_PCIE_PME BIT(24)
#define PM_ACPI_PCIE_WAK_MASK BIT(25)
#define PM_ACPI_WAKE_AS_GEVENT BIT(27)
#define PM_ACPI_NB_PME_GEVENT BIT(28)
#define PM_ACPI_RTC_WAKE_EN BIT(29)
#define PM_RST_CTRL1 0xbe
#define SLPTYPE_CONTROL_EN BIT(5)
#define PM_RST_STATUS 0xc0
#define PM_LPC_GATING 0xec
#define PM_LPC_AB_NO_BYPASS_EN BIT(2)
#define PM_LPC_A20_EN BIT(1)
#define PM_LPC_ENABLE BIT(0)
#define PM_USB_ENABLE 0xef
#define PM_USB_ALL_CONTROLLERS 0x7f
/* SMBUS MMIO offsets 0xfed80a00 */
#define SMBHSTSTAT 0x0
#define SMBHST_STAT_FAILED BIT(4)
#define SMBHST_STAT_COLLISION BIT(3)
#define SMBHST_STAT_ERROR BIT(2)
#define SMBHST_STAT_INTERRUPT BIT(1)
#define SMBHST_STAT_BUSY BIT(0)
#define SMBHST_STAT_CLEAR 0xff
#define SMBHST_STAT_NOERROR BIT(1)
#define SMBHST_STAT_VAL_BITS 0x1f
#define SMBHST_STAT_ERROR_BITS 0x1c
#define SMBSLVSTAT 0x1
#define SMBSLV_STAT_ALERT 0x20
#define SMBSLV_STAT_SHADOW2 0x10
#define SMBSLV_STAT_SHADOW1 0x08
#define SMBSLV_STAT_SLV_STS 0x04
#define SMBSLV_STAT_SLV_INIT 0x02
#define SMBSLV_STAT_SLV_BUSY 0x01
#define SMBSLV_STAT_CLEAR 0x1f
#define SMBHSTCTRL 0x2
#define SMBHST_CTRL_RST 0x80
#define SMBHST_CTRL_STRT 0x40
#define SMBHST_CTRL_QCK_RW 0x00
#define SMBHST_CTRL_BTE_RW 0x04
#define SMBHST_CTRL_BDT_RW 0x08
#define SMBHST_CTRL_WDT_RW 0x0c
#define SMBHST_CTRL_BLK_RW 0x14
#define SMBHST_CTRL_MODE_BITS 0x1c
#define SMBHST_CTRL_KILL 0x02
#define SMBHST_CTRL_IEN 0x01
#define SMBHSTCMD 0x3
#define SMBHSTADDR 0x4
#define SMBHSTDAT0 0x5
#define SMBHSTDAT1 0x6
#define SMBHSTBLKDAT 0x7
#define SMBSLVCTRL 0x8
#define SMBSLVCMD_SHADOW 0x9
#define SMBSLVEVT 0xa
#define SMBSLVDAT 0xc
#define SMBTIMING 0xe
/* FCH MISC Registers 0xfed80e00 */
#define GPP_CLK_CNTRL 0x00
#define GPP_CLK0_REQ_SHL 0
#define GPP_CLK1_REQ_SHL 2
#define GFX_CLK0_REQ_SHL 4
#define GPP_CLK2_REQ_SHL 6
#define GPP_CLK3_REQ_SHL 8
#define GFX_CLK1_REQ_SHL 10
#define GPP_CLK_REQ_MAP_MASK0 (3 << GPP_CLK0_REQ_SHL)
#define GPP_CLK_REQ_MAP_CLK0 (1 << GPP_CLK0_REQ_SHL)
#define GPP_CLK_REQ_MAP_MASK1 (3 << GPP_CLK1_REQ_SHL)
#define GPP_CLK_REQ_MAP_CLK1 (1 << GPP_CLK1_REQ_SHL)
#define GFX_CLK_REQ_MAP_MASK0 (3 << GFX_CLK0_REQ_SHL)
#define GFX_CLK_REQ_MAP_CLK0 (1 << GFX_CLK0_REQ_SHL)
#define GPP_CLK_REQ_MAP_MASK2 (3 << GPP_CLK2_REQ_SHL)
#define GPP_CLK_REQ_MAP_CLK2 (1 << GPP_CLK2_REQ_SHL)
#define GPP_CLK_REQ_MAP_MASK3 (3 << GPP_CLK3_REQ_SHL)
#define GPP_CLK_REQ_MAP_CLK3 (1 << GPP_CLK3_REQ_SHL)
#define GFX_CLK_REQ_MAP_MASK1 (3 << GPP_CLK1_REQ_SHL)
#define GFX_CLK_REQ_MAP_CLK1 (1 << GPP_CLK1_REQ_SHL)
#define MISC_CGPLL_CONFIG1 0x08
#define CG1PLL_SPREAD_SPECTRUM_ENABLE BIT(0)
#define MISC_CLK_CNTL1 0x40
#define BP_X48M0_OUTPUT_EN BIT(2) /* 1=En, unlike Hudson, Kern */
#define OSCOUT1_CLK_OUTPUT_ENB BIT(2) /* 0 = Enabled, 1 = Disabled */
#define OSCOUT2_CLK_OUTPUT_ENB BIT(7) /* 0 = Enabled, 1 = Disabled */
#define MISC_I2C0_PAD_CTRL 0xd8
#define MISC_I2C1_PAD_CTRL 0xdc
#define MISC_I2C2_PAD_CTRL 0xe0
#define MISC_I2C3_PAD_CTRL 0xe4
#define I2C_PAD_CTRL_NG_MASK (BIT(0) + BIT(1) + BIT(2) + BIT(3))
#define I2C_PAD_CTRL_NG_NORMAL 0xc
#define I2C_PAD_CTRL_RX_SEL_MASK (BIT(4) + BIT(5))
#define I2C_PAD_CTRL_RX_SHIFT 4
#define I2C_PAD_CTRL_RX_SEL_OFF (0 << I2C_PAD_CTRL_RX_SHIFT)
#define I2C_PAD_CTRL_RX_SEL_3_3V (1 << I2C_PAD_CTRL_RX_SHIFT)
#define I2C_PAD_CTRL_RX_SEL_1_8V (3 << I2C_PAD_CTRL_RX_SHIFT)
#define I2C_PAD_CTRL_PULLDOWN_EN BIT(6)
#define I2C_PAD_CTRL_FALLSLEW_MASK (BIT(7) + BIT(8))
#define I2C_PAD_CTRL_FALLSLEW_SHIFT 7
#define I2C_PAD_CTRL_FALLSLEW_STD (0 << I2C_PAD_CTRL_FALLSLEW_SHIFT)
#define I2C_PAD_CTRL_FALLSLEW_LOW (1 << I2C_PAD_CTRL_FALLSLEW_SHIFT)
#define I2C_PAD_CTRL_FALLSLEW_EN BIT(9)
#define I2C_PAD_CTRL_SPIKE_RC_EN BIT(10)
#define I2C_PAD_CTRL_SPIKE_RC_SEL BIT(11) /* 0 = 50ns, 1 = 20ns */
#define I2C_PAD_CTRL_CAP_DOWN BIT(12)
#define I2C_PAD_CTRL_CAP_UP BIT(13)
#define I2C_PAD_CTRL_RES_DOWN BIT(14)
#define I2C_PAD_CTRL_RES_UP BIT(15)
#define I2C_PAD_CTRL_BIOS_CRT_EN BIT(16)
#define I2C_PAD_CTRL_SPARE0 BIT(17)
#define I2C_PAD_CTRL_SPARE1 BIT(18)
/* FCH AOAC Registers 0xfed81e00 */
#define AOAC_DEV_D3_CTL(device) (0x40 + device * 2)
#define AOAC_DEV_D3_STATE(device) (AOAC_DEV_D3_CTL(device) + 1)
#define FCH_AOAC_DEV_CLK_GEN 0
#define FCH_AOAC_DEV_I2C2 7
#define FCH_AOAC_DEV_I2C3 8
#define FCH_AOAC_DEV_I2C4 9
#define FCH_AOAC_DEV_UART0 11
#define FCH_AOAC_DEV_UART1 12
#define FCH_AOAC_DEV_UART2 16
#define FCH_AOAC_DEV_AMBA 17
#define FCH_AOAC_DEV_UART3 26
#define FCH_AOAC_DEV_ESPI 27
/* Bit definitions for Device D3 Control AOACx0000[40...7E] step 2 */
#define FCH_AOAC_TARGET_DEVICE_STATE (BIT(0) + BIT(1))
#define FCH_AOAC_DEVICE_STATE BIT(2)
#define FCH_AOAC_PWR_ON_DEV BIT(3)
#define FCH_AOAC_SW_PWR_ON_RSTB BIT(4)
#define FCH_AOAC_SW_REF_CLK_OK BIT(5)
#define FCH_AOAC_SW_RST_B BIT(6)
#define FCH_AOAC_IS_SW_CONTROL BIT(7)
/* Bit definitions for Device D3 State AOACx0000[41...7f] step 2 */
#define FCH_AOAC_PWR_RST_STATE BIT(0)
#define FCH_AOAC_RST_CLK_OK_STATE BIT(1)
#define FCH_AOAC_RST_B_STATE BIT(2)
#define FCH_AOAC_DEV_OFF_GATING_STATE BIT(3)
#define FCH_AOAC_D3COLD BIT(4)
#define FCH_AOAC_CLK_OK_STATE BIT(5)
#define FCH_AOAC_STAT0 BIT(6)
#define FCH_AOAC_STAT1 BIT(7)
#define FCH_UART_LEGACY_DECODE 0xfedc0020
#define FCH_LEGACY_3F8_SH 3
#define FCH_LEGACY_2F8_SH 1
#define FCH_LEGACY_3E8_SH 2
#define PM1_LIMIT 16
#define GPE0_LIMIT 28
#define TOTAL_BITS(a) (8 * sizeof(a))
/* SATA Controller D11F0 */
#define SATA_MISC_CONTROL_REG 0x40
#define SATA_MISC_SUBCLASS_WREN BIT(0)
/* Register in AHCIBaseAddress (BAR5 at D11F0x24) */
#define SATA_CAPABILITIES_REG 0xfc
#define SATA_CAPABILITY_SPM BIT(12)
#define SPI_CNTRL0 0x00
#define SPI_BUSY BIT(31)
enum spi_read_mode {
SPI_READ_MODE_NORMAL33M = 0,
/* 1 is reserved. */
SPI_READ_MODE_DUAL112 = 2,
SPI_READ_MODE_QUAD114 = 3,
SPI_READ_MODE_DUAL122 = 4,
SPI_READ_MODE_QUAD144 = 5,
SPI_READ_MODE_NORMAL66M = 6,
SPI_READ_MODE_FAST_READ = 7,
};
/*
* SPI read mode is split into bits 18, 29, 30 such that [30:29:18] correspond to bits [2:0] for
* SpiReadMode.
*/
#define SPI_READ_MODE_MASK (BIT(30) | BIT(29) | BIT(18))
#define SPI_READ_MODE_UPPER_BITS(x) ((((x) >> 1) & 0x3) << 29)
#define SPI_READ_MODE_LOWER_BITS(x) (((x) & 0x1) << 18)
#define SPI_READ_MODE(x) (SPI_READ_MODE_UPPER_BITS(x) | \
SPI_READ_MODE_LOWER_BITS(x))
#define SPI_ACCESS_MAC_ROM_EN BIT(22)
#define SPI_FIFO_PTR_CLR BIT(20)
#define SPI_ARB_ENABLE BIT(19)
#define EXEC_OPCODE BIT(16)
#define SPI_FIFO 0x80
#define SPI_FIFO_DEPTH (0xc7 - SPI_FIFO)
#define SPI100_ENABLE 0x20
#define SPI_USE_SPI100 BIT(0)
/* Use SPI_SPEED_16M-SPI_SPEED_66M below for the southbridge */
#define SPI100_SPEED_CONFIG 0x22
enum spi100_speed {
SPI_SPEED_66M = 0,
SPI_SPEED_33M = 1,
SPI_SPEED_22M = 2,
SPI_SPEED_16M = 3,
SPI_SPEED_100M = 4,
SPI_SPEED_800K = 5,
};
#define SPI_SPEED_MASK 0xf
#define SPI_SPEED_MODE(x, shift) (((x) & SPI_SPEED_MASK) << (shift))
#define SPI_NORM_SPEED(x) SPI_SPEED_MODE(x, 12)
#define SPI_FAST_SPEED(x) SPI_SPEED_MODE(x, 8)
#define SPI_ALT_SPEED(x) SPI_SPEED_MODE(x, 4)
#define SPI_TPM_SPEED(x) SPI_SPEED_MODE(x, 0)
#define SPI_SPEED_CFG(n, f, a, t) (SPI_NORM_SPEED(n) | SPI_FAST_SPEED(f) | \
SPI_ALT_SPEED(a) | SPI_TPM_SPEED(t))
#define SPI100_HOST_PREF_CONFIG 0x2c
#define SPI_RD4DW_EN_HOST BIT(15)
/* IO 0xcf9 - Reset control port*/
#define FULL_RST BIT(3)
#define RST_CMD BIT(2)
#define SYS_RST BIT(1)
/* IO 0xf0 NCP Error */
#define NCP_WARM_BOOT BIT(7) /* Write-once */
typedef struct aoac_devs {
unsigned int :7;
unsigned int ic2e:1; /* 7: I2C2 */
unsigned int ic3e:1; /* 8: I2C3 */
unsigned int ic4e:1; /* 9: I2C4 */
unsigned int :1;
unsigned int ut0e:1; /* 11: UART0 */
unsigned int ut1e:1; /* 12: UART1 */
unsigned int :3;
unsigned int ut2e:1; /* 16: UART2 */
unsigned int :9;
unsigned int ut3e:1; /* 26: UART3 */
unsigned int espi:1; /* 27: ESPI */
unsigned int :4;
} __packed aoac_devs_t;
struct soc_power_reg {
uint16_t pm1_sts;
uint16_t pm1_en;
uint32_t gpe0_sts;
uint32_t gpe0_en;
uint16_t wake_from;
};
void enable_aoac_devices(void);
void sb_clk_output_48Mhz(void);
void sb_disable_4dw_burst(void);
void sb_enable(struct device *dev);
void southbridge_final(void *chip_info);
void southbridge_init(void *chip_info);
void sb_read_mode(u32 mode);
void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm);
void fch_pre_init(void);
void fch_early_init(void);
void set_uart_config(int idx);
/* Initialize all the i2c buses that are marked with early init. */
void i2c_soc_early_init(void);
/* Initialize all the i2c buses that are not marked with early init. */
void i2c_soc_init(void);
/* Allow the board to change the default I2C pad configuration */
void mainboard_i2c_override(int bus, uint32_t *pad_settings);
#endif /* __PICASSO_SB_H__ */
|
