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/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef AMD_SABRINA_AOAC_DEFS_H
#define AMD_SABRINA_AOAC_DEFS_H
/* FCH AOAC device offsets for AOAC_DEV_D3_CTL/AOAC_DEV_D3_STATE */
#define FCH_AOAC_DEV_CLK_GEN 0
#define FCH_AOAC_DEV_I2C0 5
#define FCH_AOAC_DEV_I2C1 6
#define FCH_AOAC_DEV_I2C2 7
#define FCH_AOAC_DEV_I2C3 8
#define FCH_AOAC_DEV_I2C4 9
#define FCH_AOAC_DEV_I2C5 10
#define FCH_AOAC_DEV_UART0 11
#define FCH_AOAC_DEV_UART1 12
#define FCH_AOAC_DEV_UART2 16
#define FCH_AOAC_DEV_AMBA 17
#define FCH_AOAC_DEV_UART4 20
#define FCH_AOAC_DEV_UART3 26
#define FCH_AOAC_DEV_ESPI 27
#define FCH_AOAC_DEV_EMMC 28
#endif /* AMD_SABRINA_AOAC_DEFS_H */
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