summaryrefslogtreecommitdiffstats
path: root/src/soc/intel/cannonlake/include/soc/ramstage.h
blob: 96b11298a706aed327ff3dfe72b3691e4e681bea (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
/* SPDX-License-Identifier: GPL-2.0-only */

#ifndef _SOC_RAMSTAGE_H_
#define _SOC_RAMSTAGE_H_

#include <device/device.h>
#include <fsp/api.h>
#include <fsp/util.h>

#include "../../chip.h"

void mainboard_silicon_init_params(FSP_S_CONFIG *params);
void soc_init_pre_device(void *chip_info);

#endif