blob: c8a1d841749ae703dc8b9677aa1e8ec6f0828f0b (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
|
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <device/pci.h>
#include <drivers/intel/gma/libgfxinit.h>
#include <intelblocks/early_graphics.h>
#include <soc/gpio.h>
#include <soc/pci_devs.h>
static void device_init(void)
{
/* Disable response in IO and MMIO space. */
pci_and_config16(SA_DEV_IGD, PCI_COMMAND,
~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY));
/* Program IGD Base Address Register 0. */
pci_write_config32(SA_DEV_IGD, PCI_BASE_ADDRESS_0,
CONFIG_GFX_GMA_DEFAULT_MMIO);
/* Enable response in IO and MMIO space. */
pci_or_config16(SA_DEV_IGD, PCI_COMMAND,
(PCI_COMMAND_IO | PCI_COMMAND_MEMORY));
}
__weak const struct pad_config *variant_early_graphics_gpio_table(size_t *num)
{
*num = 0;
return NULL;
}
bool early_graphics_init(void)
{
int ret;
const struct pad_config *pads;
size_t pads_num;
if (!CONFIG(MAINBOARD_USE_EARLY_LIBGFXINIT))
return false;
/* Perform minimal graphic MMIO configuration. */
device_init();
/* Optionally configure any required display related GPIOs */
pads = variant_early_graphics_gpio_table(&pads_num);
gpio_configure_pads(pads, pads_num);
/* Configure display panel. */
early_graphics_soc_panel_init();
gma_gfxinit(&ret);
return !!ret;
}
void early_graphics_stop(void)
{
if (!CONFIG(MAINBOARD_USE_EARLY_LIBGFXINIT))
return;
gma_gfxstop();
}
|
