blob: 8a15a69a236277ca3d342e01b2669476314e52b4 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
|
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <fsp/util.h>
#include <soc/romstage.h>
asmlinkage void *car_stage_c_entry(void)
{
bool s3wake = false;
console_init();
/* TODO: Add fill_powerstate and determine sleep state. */
fsp_memory_init(s3wake);
return NULL;
}
static void soc_memory_init_params(struct FSP_M_CONFIG *m_cfg)
{
/* TODO: Fill SoC specific Memory init Params */
}
void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd){
struct FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
soc_memory_init_params(m_cfg);
mainboard_memory_init_params(mupd);
}
__attribute__((weak)) void mainboard_memory_init_params(struct FSPM_UPD *mupd)
{
/* Do nothing */
}
|
