src/soc/intel/tigerlake/include/soc/romstage.h


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/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

#ifndef _SOC_ROMSTAGE_H_
#define _SOC_ROMSTAGE_H_

#include <fsp/api.h>

/* Provide a callback to allow mainboard to override the DRAM part number. */
bool mainboard_get_dram_part_num(const char **part_num, size_t *len);
void mainboard_memory_init_params(FSPM_UPD *mupd);
void systemagent_early_init(void);
void pch_init(void);

/* Board type */
enum board_type {
	BOARD_TYPE_MOBILE  = 0,
	BOARD_TYPE_DESKTOP = 1,
	BOARD_TYPE_ULT_ULX = 5,
	BOARD_TYPE_SERVER  = 7
};

#endif /* _SOC_ROMSTAGE_H_ */