1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
|
/* SPDX-License-Identifier: GPL-2.0-only */
#include <assert.h>
#include <device/device.h>
#include <device/pci.h>
#include <intelblocks/cpulib.h>
#include <soc/pci_devs.h>
#include <soc/soc_util.h>
#include <soc/util.h>
#include <pc80/mc146818rtc.h>
const struct SystemMemoryMapHob *get_system_memory_map(void)
{
size_t hob_size;
const uint8_t mem_hob_guid[16] = FSP_SYSTEM_MEMORYMAP_HOB_GUID;
const struct SystemMemoryMapHob **memmap_addr;
memmap_addr = (const struct SystemMemoryMapHob **)
fsp_find_extension_hob_by_guid(mem_hob_guid, &hob_size);
/* hob_size is the size of the 8-byte address not the hob data */
assert(memmap_addr && hob_size != 0);
/* assert the pointer to the hob is not NULL */
assert(*memmap_addr);
return *memmap_addr;
}
bool is_pcie_iio_stack_res(const STACK_RES *res)
{
return res->Personality == TYPE_UBOX_IIO;
}
bool is_ubox_stack_res(const STACK_RES *res)
{
return res->Personality == TYPE_UBOX;
}
uint8_t get_stack_busno(const uint8_t stack)
{
if (stack >= MAX_IIO_STACK) {
printk(BIOS_ERR, "%s: Stack %u does not exist!\n", __func__, stack);
return 0;
}
const pci_devfn_t dev = PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, UBOX_DECS_FUNC);
const uint16_t offset = stack / 4 ? UBOX_DECS_CPUBUSNO1_CSR : UBOX_DECS_CPUBUSNO_CSR;
return pci_io_read_config32(dev, offset) >> (8 * (stack % 4)) & 0xff;
}
uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack)
{
const IIO_UDS *hob = get_iio_uds();
assert(socket < CONFIG_MAX_SOCKET && stack < MAX_LOGIC_IIO_STACK);
return hob->PlatformData.IIO_resource[socket].StackRes[stack].BusBase;
}
uint32_t get_socket_ubox_busno(uint32_t socket)
{
if (socket == 0)
return get_stack_busno(PCU_IIO_STACK);
return get_socket_stack_busno(socket, PCU_IIO_STACK);
}
/*
* EX: CPX-SP
* Ports Stack Stack(HOB) IioConfigIou
* ==========================================
* 0 CSTACK stack 0 IOU0
* 1A..1D PSTACKZ stack 1 IOU1
* 2A..2D PSTACK1 stack 2 IOU2
* 3A..3D PSTACK2 stack 4 IOU3
*/
int soc_get_stack_for_port(int port)
{
if (port == PORT_0)
return CSTACK;
else if (port >= PORT_1A && port <= PORT_1D)
return PSTACK0;
else if (port >= PORT_2A && port <= PORT_2D)
return PSTACK1;
else if (port >= PORT_3A && port <= PORT_3D)
return PSTACK2;
else
return -1;
}
uint8_t soc_get_iio_ioapicid(int socket, int stack)
{
uint8_t ioapic_id = socket ? 0xf : 0x9;
switch (stack) {
case CSTACK:
break;
case PSTACK0:
ioapic_id += 1;
break;
case PSTACK1:
ioapic_id += 2;
break;
case PSTACK2:
ioapic_id += 3;
break;
default:
return 0xff;
}
return ioapic_id;
}
void soc_set_mrc_cold_boot_flag(bool cold_boot_required)
{
uint8_t mrc_status = cmos_read(CMOS_OFFSET_MRC_STATUS);
uint8_t new_mrc_status = (mrc_status & 0xfe) | cold_boot_required;
printk(BIOS_SPEW, "MRC status: 0x%02x want 0x%02x\n", mrc_status, new_mrc_status);
if (new_mrc_status != mrc_status) {
cmos_write(new_mrc_status, CMOS_OFFSET_MRC_STATUS);
}
}
void get_iiostack_info(struct iiostack_resource *info)
{
const IIO_UDS *hob = get_iio_uds();
// copy IIO Stack info from FSP HOB
info->no_of_stacks = 0;
for (int socket = 0, iio = 0; iio < hob->PlatformData.numofIIO; ++socket) {
if (!soc_cpu_is_enabled(socket))
continue;
iio++;
for (int x = 0; x < MAX_IIO_STACK; ++x) {
const STACK_RES *ri;
ri = &hob->PlatformData.IIO_resource[socket].StackRes[x];
if (!is_pcie_iio_stack_res(ri))
continue;
assert(info->no_of_stacks < (CONFIG_MAX_SOCKET * MAX_IIO_STACK));
memcpy(&info->res[info->no_of_stacks++], ri, sizeof(STACK_RES));
}
}
}
|
