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/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */
#include <commonlib/helpers.h>
/*
* Currently all known xeon-sp CPUs use C620 PCH. These definitions
* come from C620 datasheet (Intel Doc #336067-007US)
*/
#define HPTC_OFFSET 0x60
#define HPTC_ADDR_ENABLE_BIT (1 << 7)
#define PCH_P2SB_EPMASK0 0xb0
#define P2SB_SIZE (16 * MiB)
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