summaryrefslogtreecommitdiffstats
path: root/src/soc/mediatek/common/mt6359p.c
blob: 5a87c0d8e1b58f9bff88b77ac648073b7c10f22b (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
/* SPDX-License-Identifier: GPL-2.0-only */

#include <assert.h>
#include <console/console.h>
#include <delay.h>
#include <soc/mt6359p.h>
#include <soc/pmif.h>
#include <timer.h>

static const struct pmic_setting key_protect_setting[] = {
	{0x3A8, 0x9CA6, 0xFFFF, 0},
	{0x44A, 0xBADE, 0xFFFF, 0},
	{0xA3A, 0x4729, 0xFFFF, 0},
	{0xC58, 0x1605, 0xFFFF, 0},
	{0xC5A, 0x1706, 0xFFFF, 0},
	{0xC5C, 0x1807, 0xFFFF, 0},
	{0xFB4, 0x6359, 0xFFFF, 0},
	{0x1432, 0x5543, 0xFFFF, 0},
};

static const struct pmic_efuse efuse_setting[] = {
	{79, 0xa0e, 0x1, 0xf},
	{886, 0x198c, 0xf, 0x8},
	{890, 0x198e, 0xf, 0x0},
	{902, 0x1998, 0xf, 0x8},
	{906, 0x1998, 0xf, 0xc},
	{918, 0x19a2, 0xf, 0x8},
	{922, 0x19a2, 0xf, 0xc},
	{1014, 0x19ae, 0xf, 0x7},
	{1018, 0x19ae, 0xf, 0xb},
	{1158, 0x1a0a, 0xf, 0x7},
	{1162, 0x1a0a, 0xf, 0xb},
	{1206, 0x1a16, 0xf, 0x7},
	{1210, 0x1a16, 0xf, 0xb},
	{1254, 0x1a22, 0xf, 0x7},
	{1258, 0x1a22, 0xf, 0xb},
	{1304, 0x1a2c, 0x7, 0x4},
	{1307, 0x1a32, 0x7, 0x8},
	{1336, 0x1a34, 0x7, 0x4},
	{1339, 0x1a3a, 0x7, 0x8},
	{1683, 0x79c, 0xf, 0x4},
	{1688, 0xc8a, 0x1, 0x3},
	{1689, 0xc88, 0x1, 0x3},
	{1690, 0xc88, 0x7, 0x0},
};

static struct pmif *pmif_arb = NULL;
static void mt6359p_write(u32 reg, u32 data)
{
	pmif_arb->write(pmif_arb, 0, reg, data);
}

static u32 mt6359p_read_field(u32 reg, u32 mask, u32 shift)
{
	return pmif_arb->read_field(pmif_arb, 0, reg, mask, shift);
}

void mt6359p_write_field(u32 reg, u32 val, u32 mask, u32 shift)
{
	pmif_arb->write_field(pmif_arb, 0, reg, val, mask, shift);
}

static void pmic_set_power_hold(void)
{
	mt6359p_write_field(PMIC_PWRHOLD, 0x1, 0x1, 0);
}

static void pmic_wdt_set(void)
{
	/* [5]=1, RG_WDTRSTB_DEB */
	mt6359p_write_field(PMIC_TOP_RST_MISC_SET, 0x20, 0xFFFF, 0);
	/* [1]=0, RG_WDTRSTB_MODE */
	mt6359p_write_field(PMIC_TOP_RST_MISC_CLR, 0x02, 0xFFFF, 0);
	/* [0]=1, RG_WDTRSTB_EN */
	mt6359p_write_field(PMIC_TOP_RST_MISC_SET, 0x01, 0xFFFF, 0);
}

static void pmic_protect_key_setting(bool lock)
{
	for (int i = 0; i < ARRAY_SIZE(key_protect_setting); i++)
		mt6359p_write(key_protect_setting[i].addr,
			      lock ? 0 : key_protect_setting[i].val);
}

static int check_idle(u32 timeout, u32 addr, u32 mask)
{
	if (!wait_us(timeout, !mt6359p_read_field(addr, mask, 0)))
		return -1;

	return 0;
}

static u32 pmic_read_efuse(u32 efuse_bit, u32 mask)
{
	u32 efuse_data;
	int index, shift;

	index = efuse_bit / 16;
	shift = efuse_bit % 16;
	mt6359p_write_field(PMIC_TOP_CKHWEN_CON0, 0, 0x1, 2);
	mt6359p_write_field(PMIC_TOP_CKPDN_CON0, 0, 0x1, 4);
	mt6359p_write_field(PMIC_OTP_CON11, 1, 0x1, 0);
	mt6359p_write_field(PMIC_OTP_CON0, index * 2, 0xFF, 0);
	if (mt6359p_read_field(PMIC_OTP_CON8, 1, 0))
		mt6359p_write_field(PMIC_OTP_CON8, 0, 1, 0);
	else
		mt6359p_write_field(PMIC_OTP_CON8, 1, 1, 0);

	udelay(300);
	if (check_idle(EFUSE_WAIT_US, PMIC_OTP_CON13, EFUSE_BUSY))
		die("[%s] timeout after %d usecs\n", __func__, EFUSE_WAIT_US);

	udelay(100);

	efuse_data = mt6359p_read_field(PMIC_OTP_CON12, 0xFFFF, 0);
	efuse_data = (efuse_data >> shift) & mask;

	mt6359p_write_field(PMIC_TOP_CKHWEN_CON0, 1, 0x1, 2);
	mt6359p_write_field(PMIC_TOP_CKPDN_CON0, 1, 0x1, 4);

	return efuse_data;
}

static void pmic_efuse_setting(void)
{
	u32 efuse_data;
	struct stopwatch sw;

	stopwatch_init(&sw);

	for (int i = 0; i < ARRAY_SIZE(efuse_setting); i++) {
		efuse_data = pmic_read_efuse(efuse_setting[i].efuse_bit, efuse_setting[i].mask);
		mt6359p_write_field(efuse_setting[i].addr, efuse_data,
			efuse_setting[i].mask, efuse_setting[i].shift);
	}

	efuse_data = pmic_read_efuse(EFUSE_RG_VPA_OC_FT, 0x1);
	if (efuse_data) {
		/* restore VPA_DLC initial setting */
		mt6359p_write(PMIC_BUCK_VPA_DLC_CON0, 0x2810);
		mt6359p_write(PMIC_BUCK_VPA_DLC_CON1, 0x800);
	}

	printk(BIOS_DEBUG, "%s: Set efuses in %ld msecs\n",
	       __func__, stopwatch_duration_msecs(&sw));
}

static void pmic_wk_vs2_voter_setting(void)
{
	/*
	 *  1. Set VS2_VOTER_VOSEL = 1.35V
	 *  2. Clear VS2_VOTER
	 *  3. Set VS2_VOSEL = 1.4V
	 */
	mt6359p_write_field(PMIC_VS2_VOTER_CFG, 0x2C, 0x7F, 0);
	mt6359p_write_field(PMIC_VS2_VOTER, 0, 0xFFF, 0);
	mt6359p_write_field(PMIC_VS2_ELR0, 0x30, 0x7F, 0);
}

void mt6359p_buck_set_voltage(u32 buck_id, u32 buck_uv)
{
	u32 vol_offset, vol_reg, vol;

	if (!pmif_arb)
		die("ERROR: pmif_arb not initialized");

	switch (buck_id) {
	case MT6359P_GPU11:
		vol_offset = 400000;
		vol_reg = PMIC_VGPU11_ELR0;
		break;
	case MT6359P_SRAM_PROC1:
		vol_offset = 500000;
		vol_reg = PMIC_VSRAM_PROC1_ELR;
		break;
	case MT6359P_SRAM_PROC2:
		vol_offset = 500000;
		vol_reg = PMIC_VSRAM_PROC2_ELR;
		break;
	case MT6359P_CORE:
		vol_offset = 506250;
		vol_reg = PMIC_VCORE_ELR0;
		break;
	default:
		die("ERROR: Unknown buck_id %u", buck_id);
		return;
	};

	vol = (buck_uv - vol_offset) / 6250;
	mt6359p_write_field(vol_reg, vol, 0x7F, 0);
}

u32 mt6359p_buck_get_voltage(u32 buck_id)
{
	u32 vol_shift, vol_offset, vol_reg, vol;

	if (!pmif_arb)
		die("ERROR: pmif_arb not initialized");

	switch (buck_id) {
	case MT6359P_GPU11:
		vol_shift = 0;
		vol_offset = 400000;
		vol_reg = PMIC_VGPU11_DBG0;
		break;
	case MT6359P_SRAM_PROC1:
		vol_shift = 8;
		vol_offset = 500000;
		vol_reg = PMIC_VSRAM_PROC1_VOSEL1;
		break;
	case MT6359P_SRAM_PROC2:
		vol_shift = 8;
		vol_offset = 500000;
		vol_reg = PMIC_VSRAM_PROC2_VOSEL1;
		break;
	case MT6359P_CORE:
		vol_shift = 0;
		vol_offset = 506250;
		vol_reg = PMIC_VCORE_DBG0;
		break;
	default:
		die("ERROR: Unknown buck_id %u", buck_id);
		return 0;
	};

	vol = mt6359p_read_field(vol_reg, 0x7F, vol_shift);
	return vol_offset + vol * 6250;
}

void mt6359p_set_vm18_voltage(u32 vm18_uv)
{
	u32 reg_vol, reg_cali;

	if (!pmif_arb)
		die("ERROR: pmif_arb not initialized");

	assert(vm18_uv >= 1700000);
	assert(vm18_uv < 2000000);

	reg_vol = (vm18_uv / 1000 - VM18_VOL_OFFSET) / 100;
	reg_cali = ((vm18_uv / 1000) % 100) / 10;
	mt6359p_write(PMIC_VM18_ANA_CON0, (reg_vol << VM18_VOL_REG_SHIFT) | reg_cali);
}

u32 mt6359p_get_vm18_voltage(void)
{
	u32 reg_vol, reg_cali;

	if (!pmif_arb)
		die("ERROR: pmif_arb not initialized");

	reg_vol = 100 * mt6359p_read_field(PMIC_VM18_ANA_CON0, 0xF, VM18_VOL_REG_SHIFT);
	reg_cali = 10 * mt6359p_read_field(PMIC_VM18_ANA_CON0, 0xF, 0);
	return 1000 * (VM18_VOL_OFFSET + reg_vol + reg_cali);
}

static void init_pmif_arb(void)
{
	if (!pmif_arb) {
		pmif_arb = get_pmif_controller(PMIF_SPI, 0);
		if (!pmif_arb)
			die("ERROR: No spi device");
	}

	if (pmif_arb->is_pmif_init_done(pmif_arb))
		die("ERROR - Failed to initialize pmif spi");
}

void mt6359p_init(void)
{
	init_pmif_arb();
	pmic_set_power_hold();
	pmic_wdt_set();
	pmic_protect_key_setting(false);
	pmic_init_setting();
	pmic_lp_setting();
	pmic_efuse_setting();
	pmic_protect_key_setting(true);
	pmic_wk_vs2_voter_setting();
}