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/*
* This file is part of the coreboot project.
*
* Copyright 2018 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef SOC_MEDIATEK_MT8183_EMI_H
#define SOC_MEDIATEK_MT8183_EMI_H
#include <stdint.h>
#include <types.h>
#include <soc/dramc_common_mt8183.h>
enum DRAMC_PARAM_SOURCE {
DRAMC_PARAM_SOURCE_SDRAM_INVALID = 0,
DRAMC_PARAM_SOURCE_SDRAM_CONFIG,
DRAMC_PARAM_SOURCE_FLASH,
};
struct sdram_params {
u16 source; /* DRAMC_PARAM_SOURCE */
u16 frequency;
u8 wr_level[CHANNEL_MAX][RANK_MAX][DQS_NUMBER];
/* DUTY */
s8 duty_clk_delay[CHANNEL_MAX];
s8 duty_dqs_delay[CHANNEL_MAX][DQS_NUMBER];
/* CBT */
u8 cbt_final_vref[CHANNEL_MAX][RANK_MAX];
u8 cbt_clk_dly[CHANNEL_MAX][RANK_MAX];
u8 cbt_cmd_dly[CHANNEL_MAX][RANK_MAX];
u8 cbt_cs_dly[CHANNEL_MAX][RANK_MAX];
/* Gating */
u8 gating2T[CHANNEL_MAX][RANK_MAX][DQS_NUMBER];
u8 gating05T[CHANNEL_MAX][RANK_MAX][DQS_NUMBER];
u8 gating_fine_tune[CHANNEL_MAX][RANK_MAX][DQS_NUMBER];
u8 gating_pass_count[CHANNEL_MAX][RANK_MAX][DQS_NUMBER];
/* TX perbit */
u8 tx_vref[CHANNEL_MAX][RANK_MAX];
u16 tx_center_min[CHANNEL_MAX][RANK_MAX][DQS_NUMBER];
u16 tx_center_max[CHANNEL_MAX][RANK_MAX][DQS_NUMBER];
u16 tx_win_center[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH];
u16 tx_first_pass[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH];
u16 tx_last_pass[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH];
/* datlat */
u8 rx_datlat[CHANNEL_MAX][RANK_MAX];
/* RX perbit */
u8 rx_vref[CHANNEL_MAX];
s16 rx_firspass[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH];
u8 rx_lastpass[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH];
u32 emi_cona_val;
u32 emi_conh_val;
u32 emi_conf_val;
u32 chn_emi_cona_val[CHANNEL_MAX];
u32 cbt_mode_extern;
u16 delay_cell_unit;
};
struct dramc_param_ops;
enum {
LP4X_DDR1600,
LP4X_DDR2400,
LP4X_DDR3200,
LP4X_DDR3600,
LP4X_DDRFREQ_MAX,
};
extern const u8 phy_mapping[CHANNEL_MAX][16];
int complex_mem_test(u8 *start, unsigned int len);
size_t sdram_size(void);
const struct sdram_params *get_sdram_config(void);
void enable_emi_dcm(void);
void mt_set_emi(const struct sdram_params *freq_params);
void mt_mem_init(struct dramc_param_ops *dparam_ops);
#endif /* SOC_MEDIATEK_MT8183_EMI_H */
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