1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
|
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef _IPQ806X_CDP_H_
#define _IPQ806X_CDP_H_
#include <types.h>
unsigned int smem_get_board_machtype(void);
typedef enum {
PHY_INTERFACE_MODE_MII,
PHY_INTERFACE_MODE_GMII,
PHY_INTERFACE_MODE_SGMII,
PHY_INTERFACE_MODE_QSGMII,
PHY_INTERFACE_MODE_TBI,
PHY_INTERFACE_MODE_RMII,
PHY_INTERFACE_MODE_RGMII,
PHY_INTERFACE_MODE_RGMII_ID,
PHY_INTERFACE_MODE_RGMII_RXID,
PHY_INTERFACE_MODE_RGMII_TXID,
PHY_INTERFACE_MODE_RTBI,
PHY_INTERFACE_MODE_XGMII,
PHY_INTERFACE_MODE_NONE /* Must be last */
} phy_interface_t;
typedef struct {
unsigned int gpio;
unsigned int func;
unsigned int dir;
unsigned int pull;
unsigned int drvstr;
unsigned int enable;
} gpio_func_data_t;
typedef struct {
unsigned int m_value;
unsigned int n_value;
unsigned int d_value;
} uart_clk_mnd_t;
/* SPI Mode */
typedef enum {
NOR_SPI_MODE_0,
NOR_SPI_MODE_1,
NOR_SPI_MODE_2,
NOR_SPI_MODE_3,
} spi_mode;
/* SPI GSBI Bus number */
typedef enum {
GSBI_BUS_5 = 0,
GSBI_BUS_6,
GSBI_BUS_7,
} spi_gsbi_bus_num;
/* SPI Chip selects */
typedef enum {
SPI_CS_0 ,
SPI_CS_1,
SPI_CS_2,
SPI_CS_3,
} spi_cs;
/* Flash Types */
typedef enum {
ONLY_NAND,
ONLY_NOR,
NAND_NOR,
NOR_MMC,
} flash_desc;
#define NO_OF_DBG_UART_GPIOS 2
#define SPI_NOR_FLASH_VENDOR_MICRON 0x1
#define SPI_NOR_FLASH_VENDOR_SPANSION 0x2
/* SPI parameters */
typedef struct {
spi_mode mode;
spi_gsbi_bus_num bus_number;
spi_cs chip_select;
int vendor;
} spinorflash_params_t;
typedef struct {
unsigned int count;
uint8_t addr[7];
} ipq_gmac_phy_addr_t;
typedef struct {
unsigned int base;
int unit;
unsigned int is_macsec;
unsigned int mac_pwr0;
unsigned int mac_pwr1;
unsigned int mac_conn_to_phy;
phy_interface_t phy;
ipq_gmac_phy_addr_t phy_addr;
} ipq_gmac_board_cfg_t;
#define IPQ_GMAC_NMACS 4
enum storm_board_id {
BOARD_ID_PROTO_0 = 0,
BOARD_ID_PROTO_0_2 = 1,
BOARD_ID_WHIRLWIND = 2,
BOARD_ID_WHIRLWIND_SP5 = 3,
BOARD_ID_PROTO_0_2_NAND = 26,
};
/* Board specific parameters */
typedef struct {
#if 0
unsigned int gmac_gpio_count;
gpio_func_data_t *gmac_gpio;
ipq_gmac_board_cfg_t gmac_cfg[IPQ_GMAC_NMACS];
flash_desc flashdesc;
spinorflash_params_t flash_param;
#endif
} __packed board_ipq806x_params_t;
extern board_ipq806x_params_t *gboard_param;
#if 0
static inline int gmac_cfg_is_valid(ipq_gmac_board_cfg_t *cfg)
{
/*
* 'cfg' is valid if and only if
* unit number is non-negative and less than IPQ_GMAC_NMACS.
* 'cfg' pointer lies within the array range of
* board_ipq806x_params_t->gmac_cfg[]
*/
return ((cfg >= &gboard_param->gmac_cfg[0]) &&
(cfg < &gboard_param->gmac_cfg[IPQ_GMAC_NMACS]) &&
(cfg->unit >= 0) && (cfg->unit < IPQ_GMAC_NMACS));
}
#endif
unsigned int get_board_index(unsigned int machid);
void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned int count);
void board_nand_init(void);
#endif /* _IPQ806X_CDP_H_ */
|
