1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
|
/* This file is part of the coreboot project. */
/* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/qcom_qup_se.h>
struct qup qup[12] = {
[0] = { .regs = (void *)QUP_SERIAL0_BASE,
.pin = { GPIO(34), GPIO(35), GPIO(36), GPIO(37) },
.func = { GPIO34_FUNC_QUP0_L0, GPIO35_FUNC_QUP0_L1,
GPIO36_FUNC_QUP0_L2, GPIO37_FUNC_QUP0_L3 }
},
[1] = { .regs = (void *)QUP_SERIAL1_BASE,
.pin = { GPIO(0), GPIO(1), GPIO(2), GPIO(3),
GPIO(12), GPIO(94) },
.func = { GPIO0_FUNC_QUP0_L0, GPIO1_FUNC_QUP0_L1,
GPIO2_FUNC_QUP0_L2, GPIO3_FUNC_QUP0_L3,
GPIO12_FUNC_QUP0_L4, GPIO94_FUNC_QUP0_L5 }
},
[2] = { .regs = (void *)QUP_SERIAL2_BASE,
.pin = { GPIO(15), GPIO(16) },
.func = { GPIO15_FUNC_QUP0_L0, GPIO16_FUNC_QUP0_L1 }
},
[3] = { .regs = (void *)QUP_SERIAL3_BASE,
.pin = { GPIO(38), GPIO(39), GPIO(40), GPIO(41) },
.func = { GPIO38_FUNC_QUP0_L0, GPIO39_FUNC_QUP0_L1,
GPIO40_FUNC_QUP0_L2, GPIO41_FUNC_QUP0_L3 }
},
[4] = { .regs = (void *)QUP_SERIAL4_BASE,
.pin = { GPIO(115), GPIO(116) },
.func = { GPIO115_FUNC_QUP0_L0, GPIO116_FUNC_QUP0_L1 }
},
[5] = { .regs = (void *)QUP_SERIAL5_BASE,
.pin = { GPIO(25), GPIO(26), GPIO(27), GPIO(28) },
.func = { GPIO25_FUNC_QUP0_L0, GPIO26_FUNC_QUP0_L1,
GPIO27_FUNC_QUP0_L2, GPIO28_FUNC_QUP0_L3 }
},
[6] = { .regs = (void *)QUP_SERIAL6_BASE,
.pin = { GPIO(59), GPIO(60), GPIO(61), GPIO(62),
GPIO(68), GPIO(72) },
.func = { GPIO59_FUNC_QUP1_L0, GPIO60_FUNC_QUP1_L1,
GPIO61_FUNC_QUP1_L2, GPIO62_FUNC_QUP1_L3,
GPIO68_FUNC_QUP1_L4, GPIO72_FUNC_QUP1_L5 }
},
[7] = { .regs = (void *)QUP_SERIAL7_BASE,
.pin = { GPIO(6), GPIO(7) },
.func = { GPIO6_FUNC_QUP1_L0, GPIO7_FUNC_QUP1_L1 }
},
[8] = { .regs = (void *)QUP_SERIAL8_BASE,
.pin = { GPIO(42), GPIO(43), GPIO(44), GPIO(45) },
.func = { GPIO42_FUNC_QUP1_L0, GPIO43_FUNC_QUP1_L1,
GPIO44_FUNC_QUP1_L2, GPIO45_FUNC_QUP1_L3 }
},
[9] = { .regs = (void *)QUP_SERIAL9_BASE,
.pin = { GPIO(46), GPIO(47) },
.func = { GPIO46_FUNC_QUP1_L0, GPIO47_FUNC_QUP1_L1 }
},
[10] = { .regs = (void *)QUP_SERIAL10_BASE,
.pin = { GPIO(86), GPIO(87), GPIO(88), GPIO(89),
GPIO(90), GPIO(91) },
.func = { GPIO86_FUNC_QUP1_L0, GPIO87_FUNC_QUP1_L1,
GPIO88_FUNC_QUP1_L2, GPIO89_FUNC_QUP1_L3,
GPIO90_FUNC_QUP1_L4, GPIO91_FUNC_QUP1_L5 }
},
[11] = { .regs = (void *)QUP_SERIAL11_BASE,
.pin = { GPIO(53), GPIO(54), GPIO(55), GPIO(56) },
.func = { GPIO53_FUNC_QUP1_L0, GPIO54_FUNC_QUP1_L1,
GPIO55_FUNC_QUP1_L2, GPIO56_FUNC_QUP1_L3 }
},
};
u32 qup_wait_for_m_irq(unsigned int bus)
{
struct stopwatch sw;
unsigned int m_irq = 0;
struct qup_regs *regs = qup[bus].regs;
stopwatch_init_usecs_expire(&sw, 25);
while (!stopwatch_expired(&sw)) {
m_irq = read32(®s->geni_m_irq_status);
if (m_irq)
break;
}
return m_irq;
}
u32 qup_wait_for_s_irq(unsigned int bus)
{
struct stopwatch sw;
unsigned int s_irq = 0;
struct qup_regs *regs = qup[bus].regs;
stopwatch_init_usecs_expire(&sw, 25);
while (!stopwatch_expired(&sw)) {
s_irq = read32(®s->geni_s_irq_status);
if (s_irq)
break;
}
return s_irq;
}
static int handle_tx(unsigned int bus, const u8 *dout,
unsigned int tx_rem_bytes)
{
int max_bytes = 0;
struct qup_regs *regs = qup[bus].regs;
max_bytes = (FIFO_DEPTH - TX_WATERMARK) * BYTES_PER_FIFO_WORD;
max_bytes = MIN(tx_rem_bytes, max_bytes);
buffer_to_fifo32((void *)dout, max_bytes, ®s->geni_tx_fifon,
0, BYTES_PER_FIFO_WORD);
if (tx_rem_bytes == max_bytes)
write32(®s->geni_tx_watermark_reg, 0);
return max_bytes;
}
static int handle_rx(unsigned int bus, u8 *din, unsigned int rx_rem_bytes)
{
struct qup_regs *regs = qup[bus].regs;
u32 rx_fifo_status = read32(®s->geni_rx_fifo_status);
int rx_bytes = 0;
rx_bytes = (rx_fifo_status & RX_FIFO_WC_MSK) * BYTES_PER_FIFO_WORD;
rx_bytes = MIN(rx_rem_bytes, rx_bytes);
buffer_from_fifo32(din, rx_bytes, ®s->geni_rx_fifon,
0, BYTES_PER_FIFO_WORD);
return rx_bytes;
}
void qup_m_cancel_and_abort(unsigned int bus)
{
struct qup_regs *regs = qup[bus].regs;
struct stopwatch sw;
unsigned int m_irq;
write32(®s->geni_tx_watermark_reg, 0);
write32(®s->geni_m_cmd_ctrl_reg, M_GENI_CMD_CANCEL);
stopwatch_init_msecs_expire(&sw, 100);
do {
m_irq = qup_wait_for_m_irq(bus);
if (m_irq & M_CMD_CANCEL_EN) {
write32(®s->geni_m_irq_clear, m_irq);
break;
}
write32(®s->geni_m_irq_clear, m_irq);
} while (!stopwatch_expired(&sw));
if (!(m_irq & M_CMD_CANCEL_EN)) {
printk(BIOS_INFO, "%s:Cancel failed, Abort the operation\n",
__func__);
write32(®s->geni_m_cmd_ctrl_reg, M_GENI_CMD_ABORT);
stopwatch_init_msecs_expire(&sw, 100);
do {
m_irq = qup_wait_for_m_irq(bus);
if (m_irq & M_CMD_ABORT_EN) {
write32(®s->geni_m_irq_clear, m_irq);
break;
}
write32(®s->geni_m_irq_clear, m_irq);
} while (!stopwatch_expired(&sw));
if (!(m_irq & M_CMD_ABORT_EN))
printk(BIOS_INFO, "%s:Abort failed\n", __func__);
}
}
void qup_s_cancel_and_abort(unsigned int bus)
{
struct qup_regs *regs = qup[bus].regs;
struct stopwatch sw;
unsigned int s_irq;
u32 rx_fifo_status;
u8 buf[64]; /* FIFO size */
write32(®s->geni_tx_watermark_reg, 0);
write32(®s->geni_s_cmd_ctrl_reg, S_GENI_CMD_CANCEL);
stopwatch_init_msecs_expire(&sw, 100);
do {
s_irq = qup_wait_for_s_irq(bus);
rx_fifo_status = read32(®s->geni_rx_fifo_status);
if (rx_fifo_status & RX_LAST)
handle_rx(bus, buf, 64); /* Read whatever data available in FIFO */
if (s_irq & S_CMD_CANCEL_EN) {
write32(®s->geni_s_irq_clear, s_irq);
break;
}
write32(®s->geni_s_irq_clear, s_irq);
} while (!stopwatch_expired(&sw));
if (!(s_irq & S_CMD_CANCEL_EN)) {
printk(BIOS_INFO, "%s:Cancel failed, Abort the operation\n",
__func__);
write32(®s->geni_s_cmd_ctrl_reg, S_GENI_CMD_ABORT);
stopwatch_init_msecs_expire(&sw, 100);
do {
s_irq = qup_wait_for_s_irq(bus);
if (s_irq & S_CMD_ABORT_EN) {
write32(®s->geni_s_irq_clear, s_irq);
break;
}
write32(®s->geni_s_irq_clear, s_irq);
} while (!stopwatch_expired(&sw));
if (!(s_irq & S_CMD_ABORT_EN))
printk(BIOS_INFO, "%s:Abort failed\n", __func__);
}
}
int qup_handle_transfer(unsigned int bus, const void *dout, void *din, int size)
{
unsigned int m_irq;
struct stopwatch sw;
unsigned int rx_rem_bytes = din ? size : 0;
unsigned int tx_rem_bytes = dout ? size : 0;
struct qup_regs *regs = qup[bus].regs;
stopwatch_init_msecs_expire(&sw, 1000);
do {
m_irq = qup_wait_for_m_irq(bus);
if ((m_irq & M_RX_FIFO_WATERMARK_EN) ||
(m_irq & M_RX_FIFO_LAST_EN))
rx_rem_bytes -= handle_rx(bus, din + size
- rx_rem_bytes, rx_rem_bytes);
if (m_irq & M_TX_FIFO_WATERMARK_EN)
tx_rem_bytes -= handle_tx(bus, dout + size
- tx_rem_bytes, tx_rem_bytes);
if (m_irq & M_CMD_DONE_EN) {
write32(®s->geni_m_irq_clear, m_irq);
break;
}
write32(®s->geni_m_irq_clear, m_irq);
} while (!stopwatch_expired(&sw));
if (!(m_irq & M_CMD_DONE_EN) || tx_rem_bytes || rx_rem_bytes) {
printk(BIOS_INFO, "%s:Error: Transfer failed\n", __func__);
qup_m_cancel_and_abort(bus);
return -1;
}
return 0;
}
|
