summaryrefslogtreecommitdiffstats
path: root/src/soc/ucb/riscv/Makefile.inc
blob: 6d2c36a3405a4f1db80fae7d4d7ae9994fdf66e5 (plain)
1
2
3
4
5
6
7
8
9
ifeq ($(CONFIG_SOC_UCB_RISCV),y)

romstage-y += cbmem.c

ramstage-y += cbmem.c

ramstage-y += chip.c

endif