1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
|
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */
/* System Bus */
/* _SB.PCI0 */
/* Operating System Capabilities Method */
Method(_OSC,4)
{
/* Check for proper PCI/PCIe UUID */
If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")))
{
/* Let OS control everything */
Return (Arg3)
} Else {
CreateDWordField(Arg3,0,CDW1)
Or(CDW1,4,CDW1) // Unrecognized UUID
Return(Arg3)
}
}
/* Describe the Southbridge devices */
/* 0:11.0 - SATA */
Device(STCR) {
Name(_ADR, 0x00110000)
} /* end STCR */
/* 0:14.0 - SMBUS */
Device(SBUS) {
Name(_ADR, 0x00140000)
} /* end SBUS */
#include "usb.asl"
/* 0:14.2 - HD Audio */
#if !CONFIG(SOUTHBRIDGE_AMD_PI_KERN)
#include "audio.asl"
#endif
/* 0:14.3 - LPC */
#include "lpc.asl"
/* 0:14.7 - SD Controller */
Device(SDCN) {
Name(_ADR, 0x00140007)
} /* end SDCN */
Name(CRES, ResourceTemplate() {
/* Set the Bus number and Secondary Bus number for the PCI0 device
* The Secondary bus range for PCI0 lets the system
* know what bus values are allowed on the downstream
* side of this PCI bus if there is a PCI-PCI bridge.
* PCI busses can have 256 secondary busses which
* range from [0-0xFF] but they do not need to be
* sequential.
*/
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, /* address granularity */
0x0000, /* range minimum */
0x00FF, /* range maximum */
0x0000, /* translation */
0x0100, /* length */
,, PSB0) /* ResourceSourceIndex, ResourceSource, DescriptorName */
IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
0x0000, /* address granularity */
0x0000, /* range minimum */
0x0CF7, /* range maximum */
0x0000, /* translation */
0x0CF8 /* length */
)
WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
0x0000, /* address granularity */
0x03B0, /* range minimum */
0x03DF, /* range maximum */
0x0000, /* translation */
0x0030 /* length */
)
WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
0x0000, /* address granularity */
0x0D00, /* range minimum */
0xFFFF, /* range maximum */
0x0000, /* translation */
0xF300 /* length */
)
Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
/* memory space for PCI BARs below 4GB */
Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
}) /* End Name(_SB.PCI0.CRES) */
Method(_CRS, 0) {
/* DBGO("\\_SB\\PCI0\\_CRS\n") */
CreateDWordField(CRES, ^MMIO._BAS, MM1B)
CreateDWordField(CRES, ^MMIO._LEN, MM1L)
/*
* Declare memory between TOM1 and 4GB as available
* for PCI MMIO.
* Use ShiftLeft to avoid 64bit constant (for XP).
* This will work even if the OS does 32bit arithmetic, as
* 32bit (0x00000000 - TOM1) will wrap and give the same
* result as 64bit (0x100000000 - TOM1).
*/
Store(TOM1, MM1B)
ShiftLeft(0x10000000, 4, Local0)
Subtract(Local0, TOM1, Local0)
Store(Local0, MM1L)
Return(CRES) /* note to change the Name buffer */
} /* end of Method(_SB.PCI0._CRS) */
#if CONFIG(HUDSON_IMC_FWM)
/* TODO: It is unstable.
* might be fixed by restructuring
*/
#include "acpi/AmdImc.asl" /* Hudson IMC function */
#endif
/*
*
* FIRST METHOD CALLED UPON BOOT
*
* 1. If debugging, print current OS and ACPI interpreter.
* 2. Get PCI Interrupt routing from ACPI VSM, this
* value is based on user choice in BIOS setup.
*/
Method(_INI, 0) {
/* DBGO("\\_SB\\_INI\n") */
/* DBGO(" DSDT.ASL code from ") */
/* DBGO(__DATE__) */
/* DBGO(" ") */
/* DBGO(__TIME__) */
/* DBGO("\n Sleep states supported: ") */
/* DBGO("\n") */
/* DBGO(" \\_OS=") */
/* DBGO(\_OS) */
/* DBGO("\n \\_REV=") */
/* DBGO(\_REV) */
/* DBGO("\n") */
/* Determine the OS we're running on */
OSFL()
#if CONFIG(HUDSON_IMC_FWM)
#if CONFIG(ACPI_ENABLE_THERMAL_ZONE)
ITZE() /* enable IMC Fan Control*/
#endif
#endif
} /* End Method(_SB._INI) */
Method(OSFL, 0){
if (LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */
if (CondRefOf(\_OSI))
{
Store(1, OSVR) /* Assume some form of XP */
if (\_OSI("Windows 2006")) /* Vista */
{
Store(2, OSVR)
}
} else {
If(WCMP(\_OS,"Linux")) {
Store(3, OSVR) /* Linux */
} Else {
Store(4, OSVR) /* Gotta be WinCE */
}
}
Return(OSVR)
}
|
