summaryrefslogtreecommitdiffstats
path: root/src/superio/smsc/lpc47b397/early_gpio.c
blob: 4da18eaa98c4addfb838fe428331f811524e4069 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
/*
 * This file is part of the coreboot project.
 *
 * Copyright (C) 2000 AG Electronics Ltd.
 * Copyright (C) 2003-2004 Linux Networx
 * Copyright (C) 2004 Tyan
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc.
 */

static void lpc47b397_gpio_offset_out(u16 iobase, u16 offset, u8 value)
{
	outb(value, iobase + offset);
}

static u8 lpc47b397_gpio_offset_in(u16 iobase, u16 offset)
{
	return inb(iobase+offset);
}

#if 0
/* For GP60-GP64, GP66-GP85. */
#define LPC47B397_GPIO_CNTL_INDEX 0x70
#define LPC47B397_GPIO_CNTL_DATA 0x71

static void lpc47b397_gpio_index_out(u16 iobase, u8 index, u8 value)
{
	outb(index, iobase + LPC47B397_GPIO_CNTL_INDEX);
	outb(value, iobase + LPC47B397_GPIO_CNTL_DATA);
}

static u8 lpc47b397_gpio_index_in(u16 iobase, u8 index)
{
	outb(index, iobase + LPC47B397_GPIO_CNTL_INDEX);
	return inb(iobase + LPC47B397_GPIO_CNTL_DATA);
}
#endif