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| author | Zeng, Star <star.zeng@intel.com> | 2021-10-21 11:28:20 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2021-10-28 02:30:46 +0000 |
| commit | bb146ce32dd8edc463e792554351e50b9e5b769f (patch) | |
| tree | edc64dafc66ff67ba326fc0f829055542e43ce8a | |
| parent | 9a95d11023ac2f2ee49a2958cf80658270442c42 (diff) | |
| download | edk2-bb146ce32dd8edc463e792554351e50b9e5b769f.tar.gz edk2-bb146ce32dd8edc463e792554351e50b9e5b769f.tar.bz2 edk2-bb146ce32dd8edc463e792554351e50b9e5b769f.zip | |
MdePkg Cpuid.h: Define CPUID.(EAX=7,ECX=0):EDX[30]
This patch follows new Intel SDM to define CPUID.(EAX=7,ECX=0):EDX[30].
Signed-off-by: Star Zeng <star.zeng@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Ray Ni <ray.ni@intel.com>
| -rw-r--r-- | MdePkg/Include/Register/Intel/Cpuid.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/MdePkg/Include/Register/Intel/Cpuid.h b/MdePkg/Include/Register/Intel/Cpuid.h index 6f77e174c1..5ec85ba561 100644 --- a/MdePkg/Include/Register/Intel/Cpuid.h +++ b/MdePkg/Include/Register/Intel/Cpuid.h @@ -1587,9 +1587,9 @@ typedef union { ///
UINT32 EnumeratesSupportForCapability:1;
///
- /// [Bit 30] Reserved.
+ /// [Bit 30] Enumerates support for the IA32_CORE_CAPABILITIES MSR.
///
- UINT32 Reserved3:1;
+ UINT32 EnumeratesSupportForCoreCapabilitiesMsr:1;
///
/// [Bit 31] Enumerates support for Speculative Store Bypass Disable (SSBD).
/// Processors that set this bit sup-port the IA32_SPEC_CTRL MSR. They allow
|