diff options
| author | Eric Dong <eric.dong@intel.com> | 2017-08-02 18:28:00 +0800 |
|---|---|---|
| committer | Eric Dong <eric.dong@intel.com> | 2017-08-07 15:28:12 +0800 |
| commit | ff481bc5c60f05149f1679ab657bf610afc55f37 (patch) | |
| tree | f932061824a739c74c25690b940af1300e145937 | |
| parent | c894f83fe35948f02b38fcc57c35998d1b88c14d (diff) | |
| download | edk2-ff481bc5c60f05149f1679ab657bf610afc55f37.tar.gz edk2-ff481bc5c60f05149f1679ab657bf610afc55f37.tar.bz2 edk2-ff481bc5c60f05149f1679ab657bf610afc55f37.zip | |
Vlv2TbltDevicePkg: Enhance get mtrr mask logic.
In order to not use the deprecated macro, refine
get mtrr mask value logic.
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: David Wei <david.wei@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
| -rw-r--r-- | Vlv2TbltDevicePkg/PlatformInitPei/MemoryPeim.c | 45 |
1 files changed, 38 insertions, 7 deletions
diff --git a/Vlv2TbltDevicePkg/PlatformInitPei/MemoryPeim.c b/Vlv2TbltDevicePkg/PlatformInitPei/MemoryPeim.c index 99bdeb11f9..5a18a3fe1e 100644 --- a/Vlv2TbltDevicePkg/PlatformInitPei/MemoryPeim.c +++ b/Vlv2TbltDevicePkg/PlatformInitPei/MemoryPeim.c @@ -70,6 +70,34 @@ GetMemorySize ( );
+/**
+ Initializes the valid address mask for MTRRs.
+
+ This function initializes the valid bits mask and valid address mask for MTRRs.
+
+**/
+UINT64
+InitializeAddressMtrrMask (
+ VOID
+ )
+{
+ UINT32 RegEax;
+ UINT8 PhysicalAddressBits;
+ UINT64 ValidMtrrBitsMask;
+
+ AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
+
+ if (RegEax >= 0x80000008) {
+ AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
+
+ PhysicalAddressBits = (UINT8) RegEax;
+ } else {
+ PhysicalAddressBits = 36;
+ }
+
+ ValidMtrrBitsMask = LShiftU64 (1, PhysicalAddressBits) - 1;
+ return (ValidMtrrBitsMask & 0xfffffffffffff000ULL);
+}
EFI_STATUS
EFIAPI
@@ -89,6 +117,7 @@ SetPeiCacheMode ( UINT64 HighMemoryLength;
UINT8 Index;
MTRR_SETTINGS MtrrSetting;
+ UINT64 ValidMtrrAddressMask;
//
// Load Cache PPI
@@ -124,6 +153,8 @@ SetPeiCacheMode ( &BootMode
);
+ ValidMtrrAddressMask = InitializeAddressMtrrMask ();
+
//
// Determine memory usage
//
@@ -166,15 +197,15 @@ SetPeiCacheMode ( //
Index = 0;
MtrrSetting.Variables.Mtrr[0].Base = (FixedPcdGet32 (PcdFlashAreaBaseAddress) | CacheWriteProtected);
- MtrrSetting.Variables.Mtrr[0].Mask = ((~((UINT64)(FixedPcdGet32 (PcdFlashAreaSize) - 1))) & MTRR_LIB_CACHE_VALID_ADDRESS) | MTRR_LIB_CACHE_MTRR_ENABLED;
+ MtrrSetting.Variables.Mtrr[0].Mask = ((~((UINT64)(FixedPcdGet32 (PcdFlashAreaSize) - 1))) & ValidMtrrAddressMask) | MTRR_LIB_CACHE_MTRR_ENABLED;
Index ++;
MemOverflow =0;
while (MaxMemoryLength > MemOverflow){
- MtrrSetting.Variables.Mtrr[Index].Base = (MemOverflow & MTRR_LIB_CACHE_VALID_ADDRESS) | CacheWriteBack;
+ MtrrSetting.Variables.Mtrr[Index].Base = (MemOverflow & ValidMtrrAddressMask) | CacheWriteBack;
MemoryLength = MaxMemoryLength - MemOverflow;
MemoryLength = GetPowerOfTwo64 (MemoryLength);
- MtrrSetting.Variables.Mtrr[Index].Mask = ((~(MemoryLength - 1)) & MTRR_LIB_CACHE_VALID_ADDRESS) | MTRR_LIB_CACHE_MTRR_ENABLED;
+ MtrrSetting.Variables.Mtrr[Index].Mask = ((~(MemoryLength - 1)) & ValidMtrrAddressMask) | MTRR_LIB_CACHE_MTRR_ENABLED;
MemOverflow += MemoryLength;
Index++;
@@ -185,15 +216,15 @@ SetPeiCacheMode ( while (MaxMemoryLength != MemoryLength) {
MemoryLengthUc = GetPowerOfTwo64 (MaxMemoryLength - MemoryLength);
- MtrrSetting.Variables.Mtrr[Index].Base = ((MaxMemoryLength - MemoryLengthUc) & MTRR_LIB_CACHE_VALID_ADDRESS) | CacheUncacheable;
- MtrrSetting.Variables.Mtrr[Index].Mask= ((~(MemoryLengthUc - 1)) & MTRR_LIB_CACHE_VALID_ADDRESS) | MTRR_LIB_CACHE_MTRR_ENABLED;
+ MtrrSetting.Variables.Mtrr[Index].Base = ((MaxMemoryLength - MemoryLengthUc) & ValidMtrrAddressMask) | CacheUncacheable;
+ MtrrSetting.Variables.Mtrr[Index].Mask= ((~(MemoryLengthUc - 1)) & ValidMtrrAddressMask) | MTRR_LIB_CACHE_MTRR_ENABLED;
MaxMemoryLength -= MemoryLengthUc;
Index++;
}
MemOverflow =0x100000000;
while (HighMemoryLength > 0) {
- MtrrSetting.Variables.Mtrr[Index].Base = (MemOverflow & MTRR_LIB_CACHE_VALID_ADDRESS) | CacheWriteBack;
+ MtrrSetting.Variables.Mtrr[Index].Base = (MemOverflow & ValidMtrrAddressMask) | CacheWriteBack;
MemoryLength = HighMemoryLength;
MemoryLength = GetPowerOfTwo64 (MemoryLength);
@@ -201,7 +232,7 @@ SetPeiCacheMode ( MemoryLength = MemOverflow;
}
- MtrrSetting.Variables.Mtrr[Index].Mask = ((~(MemoryLength - 1)) & MTRR_LIB_CACHE_VALID_ADDRESS) | MTRR_LIB_CACHE_MTRR_ENABLED;
+ MtrrSetting.Variables.Mtrr[Index].Mask = ((~(MemoryLength - 1)) & ValidMtrrAddressMask) | MTRR_LIB_CACHE_MTRR_ENABLED;
MemOverflow += MemoryLength;
HighMemoryLength -= MemoryLength;
|