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authorGiri P Mudusuru <giri.p.mudusuru@intel.com>2016-10-17 20:10:16 -0700
committerGiri P Mudusuru <giri.p.mudusuru@intel.com>2016-10-18 03:32:41 -0700
commitd4a9b90fa7179f1c8c58c601160acf9ffc98f321 (patch)
treee4bf23854dd258aa380d42bd8e521bbf66dce525
parentaaba2a44c24e8c688343bda15e915be9ae24056c (diff)
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IntelSiliconPkg: Fixed bug in IgdOpregion spec
Spec documents Mailbox3 - RM31 size as 0x45(69) instead of 0x46(70) Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
-rw-r--r--IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion.h4
1 files changed, 3 insertions, 1 deletions
diff --git a/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion.h b/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion.h
index c66a45261a..fd6f813a94 100644
--- a/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion.h
+++ b/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion.h
@@ -4,6 +4,8 @@
https://01.org/sites/default/files/documentation/skl_opregion_rev0p5.pdf
+ @note Fixed bug in the spec Mailbox3 - RM31 size from 0x45(69) to 0x46(70)
+
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -116,7 +118,7 @@ typedef struct {
UINT64 FDSS; ///< Offset 0x3AA DSS Buffer address allocated for IFFS feature
UINT32 FDSP; ///< Offset 0x3B2 Size of DSS buffer
UINT32 STAT; ///< Offset 0x3B6 State Indicator
- UINT8 RM31[0x45]; ///< Offset 0x3BA - 0x3FF Reserved Must be zero
+ UINT8 RM31[0x46]; ///< Offset 0x3BA - 0x3FF Reserved Must be zero. Bug in spec 0x45(69)
} IGD_OPREGION_MBOX3;
///