UefiCpuPkg/CpuPageTableLib/TestCase: Refine test case for PAE paging.

Refine test case:
1. Check PAE paging reserved bits is zero.
2. Set stack as random value.

Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>

2 files changed, 34 insertions, 4 deletions

diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c
index f7a77d00e7..9ac3188be0 100644
--- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c
+++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomTest.c
@@ -139,6 +139,23 @@ RandomBoolean (
 }

 

 /**

+  Set 8K stack as random value.

+**/

+VOID

+SetRandomStack (

+  VOID

+  )

+{

+  UINT64  Buffer[SIZE_1KB];

+  UINTN   Index;

+

+  for (Index = 0; Index < SIZE_1KB; Index++) {

+    Buffer[Index] = Random64 (0, MAX_UINT64);

+    Buffer[Index] = Buffer[Index];

+  }

+}

+

+/**

   Check if the Page table entry is valid

 

   @param[in]   PagingEntry    The entry in page table to verify

@@ -670,6 +687,7 @@ SingleMapEntryTest (
   IsNotPresent              = FALSE;

   IsModified                = FALSE;

 

+  SetRandomStack ();

   GenerateSingleRandomMapEntry (MaxAddress, MapEntrys);

   LastMapEntry = &MapEntrys->Maps[MapsIndex];

   Status       = PageTableParse (*PageTable, PagingMode, NULL, &MapCount);

@@ -1039,7 +1057,11 @@ TestCaseforRandomTest (
   mSupportedBit.Bits.Pat            = 1;

   mSupportedBit.Bits.Global         = 1;

   mSupportedBit.Bits.ProtectionKey  = 0xF;

-  mSupportedBit.Bits.Nx             = 1;

+  if (((CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT *)Context)->PagingMode == PagingPae) {

+    mSupportedBit.Bits.ProtectionKey = 0;

+  }

+

+  mSupportedBit.Bits.Nx = 1;

 

   mRandomOption = ((CPU_PAGE_TABLE_LIB_RANDOM_TEST_CONTEXT *)Context)->RandomOption;

   mNumberIndex  = 0;

diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c
index 67776255c2..d2c50a6c8a 100644
--- a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c
+++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c
@@ -9,6 +9,7 @@
 #include "CpuPageTableLibUnitTest.h"

 #include "../CpuPageTable.h"

 

+#define IA32_PAE_RESERVED_MASK  0x7FF0000000000000ull

 //

 // Global Data to validate if the page table is legal

 // mValidMaskNoLeaf[0] is not used

@@ -95,6 +96,7 @@ InitGlobalData (
   @param[in]   Level          the level of PagingEntry.

   @param[in]   MaxLeafLevel   Max leaf entry level.

   @param[in]   LinearAddress  The linear address verified.

+  @param[in]   PagingMode     The paging mode.

 

   @retval  Leaf entry.

 **/

@@ -103,13 +105,18 @@ IsPageTableEntryValid (
   IN IA32_PAGING_ENTRY  *PagingEntry,

   IN UINTN              Level,

   IN UINTN              MaxLeafLevel,

-  IN UINT64             Address

+  IN UINT64             Address,

+  IN PAGING_MODE        PagingMode

   )

 {

   UINT64             Index;

   IA32_PAGING_ENTRY  *ChildPageEntry;

   UNIT_TEST_STATUS   Status;

 

+  if (PagingMode == PagingPae) {

+    UT_ASSERT_EQUAL (PagingEntry->Uint64 & IA32_PAE_RESERVED_MASK, 0);

+  }

+

   if (PagingEntry->Pce.Present == 0) {

     return UNIT_TEST_PASSED;

   }

@@ -142,7 +149,7 @@ IsPageTableEntryValid (
 

   ChildPageEntry = (IA32_PAGING_ENTRY  *)(UINTN)(IA32_PNLE_PAGE_TABLE_BASE_ADDRESS (&PagingEntry->Pnle));

   for (Index = 0; Index < 512; Index++) {

-    Status = IsPageTableEntryValid (&ChildPageEntry[Index], Level-1, MaxLeafLevel, Address + (Index<<(9*(Level-1) + 3)));

+    Status = IsPageTableEntryValid (&ChildPageEntry[Index], Level-1, MaxLeafLevel, Address + (Index<<(9*(Level-1) + 3)), PagingMode);

     if (Status != UNIT_TEST_PASSED) {

       return Status;

     }

@@ -190,9 +197,10 @@ IsPageTableValid (
     if (PagingMode == PagingPae) {

       UT_ASSERT_EQUAL (PagingEntry[Index].PdptePae.Bits.MustBeZero, 0);

       UT_ASSERT_EQUAL (PagingEntry[Index].PdptePae.Bits.MustBeZero2, 0);

+      UT_ASSERT_EQUAL (PagingEntry[Index].PdptePae.Bits.MustBeZero3, 0);

     }

 

-    Status = IsPageTableEntryValid (&PagingEntry[Index], MaxLevel, MaxLeafLevel, Index << (9 * MaxLevel + 3));

+    Status = IsPageTableEntryValid (&PagingEntry[Index], MaxLevel, MaxLeafLevel, Index << (9 * MaxLevel + 3), PagingMode);

     if (Status != UNIT_TEST_PASSED) {

       return Status;

     }