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| author | Sunil V L <sunilvl@ventanamicro.com> | 2024-01-03 11:13:47 +0530 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2024-01-11 12:07:42 +0000 |
| commit | fd629ef6e3dc894ddcfefe21542190f26c8c5c65 (patch) | |
| tree | 751d8b332477100fd2ef9dd1f4f60c251659062c | |
| parent | 889535caf8869e3d4818b75f95f2fc910c84a4d2 (diff) | |
| download | edk2-fd629ef6e3dc894ddcfefe21542190f26c8c5c65.tar.gz edk2-fd629ef6e3dc894ddcfefe21542190f26c8c5c65.tar.bz2 edk2-fd629ef6e3dc894ddcfefe21542190f26c8c5c65.zip | |
MdePkg.dec: RISC-V: Define override bit for Sstc extension
Define the BIT 1 as the override bit for Sstc extension. This will be
used by the timer driver to decide whether to use SBI calls or direct
CSR access to configure the timer.
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Andrei Warkentin <andrei.warkentin@intel.com>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
| -rw-r--r-- | MdePkg/MdePkg.dec | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index 2ee112cc08..0459418906 100644 --- a/MdePkg/MdePkg.dec +++ b/MdePkg/MdePkg.dec @@ -2405,6 +2405,8 @@ # Configurability to override RISC-V CPU Features
# BIT 0 = Cache Management Operations. This bit is relevant only if
# previous stage has feature enabled and user wants to disable it.
+ # BIT 1 = Supervisor Time Compare (Sstc). This bit is relevant only if
+ # previous stage has feature enabled and user wants to disable it.
#
gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0xFFFFFFFFFFFFFFFF|UINT64|0x69
|