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| author | Tan, Dun <dun.tan@intel.com> | 2023-01-03 13:56:17 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2023-01-03 06:41:11 +0000 |
| commit | b670700ddf5eb1dd958d60eb4f2a51e0636206f9 (patch) | |
| tree | a0dd7fc968848ecf918a2ab40abc037a54b01f2c | |
| parent | bbd30066e137c036db140b6e58e6e172e2827eb3 (diff) | |
| download | edk2-b670700ddf5eb1dd958d60eb4f2a51e0636206f9.tar.gz edk2-b670700ddf5eb1dd958d60eb4f2a51e0636206f9.tar.bz2 edk2-b670700ddf5eb1dd958d60eb4f2a51e0636206f9.zip | |
UefiCpuPkg/PiSmmCpuDxeSmm:Fix PF issue caused by smm page table code
When setting new page table pool to RO, only disable/enable WP when
Cr0.WP has been set to 1 to fix potential PF caused by b822be1a20
(UefiCpuPkg/PiSmmCpuDxeSmm: Introduce page table pool mechanism).
With previous code, if someone want to modify the page table and
Cr0.WP has been cleared before modify page table, Cr0.WP may be set
to 1 again since new pool may be generated during this process
Then PF fault may happens.
Signed-off-by: Dun Tan <dun.tan@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
| -rw-r--r-- | UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 41 |
1 files changed, 27 insertions, 14 deletions
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c index 4bb23f6920..834a756061 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c @@ -67,8 +67,10 @@ InitializePageTablePool ( IN UINTN PoolPages
)
{
- VOID *Buffer;
- BOOLEAN CetEnabled;
+ VOID *Buffer;
+ BOOLEAN CetEnabled;
+ BOOLEAN WpEnabled;
+ IA32_CR0 Cr0;
//
// Always reserve at least PAGE_TABLE_POOL_UNIT_PAGES, including one page for
@@ -106,21 +108,32 @@ InitializePageTablePool ( //
if (mIsReadOnlyPageTable) {
CetEnabled = ((AsmReadCr4 () & CR4_CET_ENABLE) != 0) ? TRUE : FALSE;
- if (CetEnabled) {
- //
- // CET must be disabled if WP is disabled.
- //
- DisableCet ();
+ Cr0.UintN = AsmReadCr0 ();
+ WpEnabled = (Cr0.Bits.WP != 0) ? TRUE : FALSE;
+ if (WpEnabled) {
+ if (CetEnabled) {
+ //
+ // CET must be disabled if WP is disabled. Disable CET before clearing CR0.WP.
+ //
+ DisableCet ();
+ }
+
+ Cr0.Bits.WP = 0;
+ AsmWriteCr0 (Cr0.UintN);
}
- AsmWriteCr0 (AsmReadCr0 () & ~CR0_WP);
SmmSetMemoryAttributes ((EFI_PHYSICAL_ADDRESS)(UINTN)Buffer, EFI_PAGES_TO_SIZE (PoolPages), EFI_MEMORY_RO);
- AsmWriteCr0 (AsmReadCr0 () | CR0_WP);
- if (CetEnabled) {
- //
- // re-enable CET.
- //
- EnableCet ();
+ if (WpEnabled) {
+ Cr0.UintN = AsmReadCr0 ();
+ Cr0.Bits.WP = 1;
+ AsmWriteCr0 (Cr0.UintN);
+
+ if (CetEnabled) {
+ //
+ // re-enable CET.
+ //
+ EnableCet ();
+ }
}
}
|