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| author | Jiaxin Wu <jiaxin.wu@intel.com> | 2023-04-19 15:31:46 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2023-05-31 04:48:36 +0000 |
| commit | 0d382976c29036f3397b1e5cf6dca87fc97949bb (patch) | |
| tree | 548f2af200029be324754e76d83ab062c0361841 | |
| parent | 56ad09ba75bef5f095a1a48e365d65195ba45d10 (diff) | |
| download | edk2-0d382976c29036f3397b1e5cf6dca87fc97949bb.tar.gz edk2-0d382976c29036f3397b1e5cf6dca87fc97949bb.tar.bz2 edk2-0d382976c29036f3397b1e5cf6dca87fc97949bb.zip | |
MdeModulePkg/DxeIpl: Align Page table Level setting with previous level.
System paging 5 level enabled or not can be checked via CR4.LA57, system
preferred Page table Level (PcdUse5LevelPageTable) must align with previous
level for 64bit long mode.
This patch is to do the wise check:
If cpu has already run in 64bit long mode PEI, Page table Level in DXE
must align with previous level.
If cpu runs in 32bit protected mode PEI, Page table Level in DXE is decided
by PCD and feature capability.
Cc: Dandan Bi <dandan.bi@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Zeng Star <star.zeng@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
| -rw-r--r-- | MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c | 36 |
1 files changed, 24 insertions, 12 deletions
diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c index 18b121d768..980c2002d4 100644 --- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c +++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c @@ -739,18 +739,30 @@ CreateIdentityMappingPageTables ( }
}
- Page5LevelSupport = FALSE;
- if (PcdGetBool (PcdUse5LevelPageTable)) {
- AsmCpuidEx (
- CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
- CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO,
- NULL,
- NULL,
- &EcxFlags.Uint32,
- NULL
- );
- if (EcxFlags.Bits.FiveLevelPage != 0) {
- Page5LevelSupport = TRUE;
+ if (sizeof (UINTN) == sizeof (UINT64)) {
+ //
+ // If cpu has already run in 64bit long mode PEI, Page table Level in DXE must align with previous level.
+ //
+ Cr4.UintN = AsmReadCr4 ();
+ Page5LevelSupport = (Cr4.Bits.LA57 != 0);
+ ASSERT (PcdGetBool (PcdUse5LevelPageTable) == Page5LevelSupport);
+ } else {
+ //
+ // If cpu runs in 32bit protected mode PEI, Page table Level in DXE is decided by PCD and feature capability.
+ //
+ Page5LevelSupport = FALSE;
+ if (PcdGetBool (PcdUse5LevelPageTable)) {
+ AsmCpuidEx (
+ CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
+ CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO,
+ NULL,
+ NULL,
+ &EcxFlags.Uint32,
+ NULL
+ );
+ if (EcxFlags.Bits.FiveLevelPage != 0) {
+ Page5LevelSupport = TRUE;
+ }
}
}
|