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| author | Ruiyu Ni <ruiyu.ni@intel.com> | 2018-08-02 09:57:17 +0800 |
|---|---|---|
| committer | Ruiyu Ni <ruiyu.ni@intel.com> | 2018-10-17 11:03:58 +0800 |
| commit | 7fb7259fc0ef9dc25fc17f437658562f0d6f9595 (patch) | |
| tree | fd323c44b4f2fc661eb68fd2943fe74e8f931e6d | |
| parent | 70c3c2370a2aefe71cf0f6c1a1e063f7d74e1d79 (diff) | |
| download | edk2-7fb7259fc0ef9dc25fc17f437658562f0d6f9595.tar.gz edk2-7fb7259fc0ef9dc25fc17f437658562f0d6f9595.tar.bz2 edk2-7fb7259fc0ef9dc25fc17f437658562f0d6f9595.zip | |
MdeModulePkg/Usb: Make sure data from HW is no more than expected
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Reviewed-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
| -rw-r--r-- | MdeModulePkg/Bus/Pci/EhciDxe/EhciSched.c | 9 | ||||
| -rw-r--r-- | MdeModulePkg/Bus/Pci/UhciDxe/UhciSched.c | 7 | ||||
| -rw-r--r-- | MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c | 9 |
3 files changed, 16 insertions, 9 deletions
diff --git a/MdeModulePkg/Bus/Pci/EhciDxe/EhciSched.c b/MdeModulePkg/Bus/Pci/EhciDxe/EhciSched.c index fea6f47f4c..168280be81 100644 --- a/MdeModulePkg/Bus/Pci/EhciDxe/EhciSched.c +++ b/MdeModulePkg/Bus/Pci/EhciDxe/EhciSched.c @@ -1009,9 +1009,12 @@ EhcMonitorAsyncRequests ( ProcBuf = NULL;
if (Urb->Result == EFI_USB_NOERROR) {
- ASSERT (Urb->Completed <= Urb->DataLen);
-
- ProcBuf = AllocatePool (Urb->Completed);
+ //
+ // Make sure the data received from HW is no more than expected.
+ //
+ if (Urb->Completed <= Urb->DataLen) {
+ ProcBuf = AllocatePool (Urb->Completed);
+ }
if (ProcBuf == NULL) {
EhcUpdateAsyncRequest (Ehc, Urb);
diff --git a/MdeModulePkg/Bus/Pci/UhciDxe/UhciSched.c b/MdeModulePkg/Bus/Pci/UhciDxe/UhciSched.c index 90f010c998..f7510f3ec0 100644 --- a/MdeModulePkg/Bus/Pci/UhciDxe/UhciSched.c +++ b/MdeModulePkg/Bus/Pci/UhciDxe/UhciSched.c @@ -2,7 +2,7 @@ The EHCI register operation routines.
-Copyright (c) 2007 - 2013, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -1001,11 +1001,12 @@ UhciMonitorAsyncReqList ( //
// Copy the data to temporary buffer if there are some
- // data transferred. We may have zero-length packet
+ // data transferred. We may have zero-length packet.
+ // Make sure the data received from HW is no more than expected.
//
Data = NULL;
- if (QhResult.Complete != 0) {
+ if ((QhResult.Complete != 0) && (QhResult.Complete <= AsyncReq->DataLen)) {
Data = AllocatePool (QhResult.Complete);
if (Data == NULL) {
diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c index 6a2ef4cd5d..166c44bf5e 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c @@ -1556,9 +1556,12 @@ XhcMonitorAsyncRequests ( //
ProcBuf = NULL;
if (Urb->Result == EFI_USB_NOERROR) {
- ASSERT (Urb->Completed <= Urb->DataLen);
-
- ProcBuf = AllocateZeroPool (Urb->Completed);
+ //
+ // Make sure the data received from HW is no more than expected.
+ //
+ if (Urb->Completed <= Urb->DataLen) {
+ ProcBuf = AllocateZeroPool (Urb->Completed);
+ }
if (ProcBuf == NULL) {
XhcUpdateAsyncRequest (Xhc, Urb);
|