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| author | Heinrich Schuchardt <heinrich.schuchardt@canonical.com> | 2024-09-16 23:12:18 +0200 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2024-10-04 04:53:21 +0000 |
| commit | 91d806917fd2be763f067a58ef05fadcf43efab1 (patch) | |
| tree | 698fad423f4d8560e74150e141b32d75c5cb44e3 | |
| parent | f8c738577f813bbe6cb017cfbb29b70582ab32b4 (diff) | |
| download | edk2-91d806917fd2be763f067a58ef05fadcf43efab1.tar.gz edk2-91d806917fd2be763f067a58ef05fadcf43efab1.tar.bz2 edk2-91d806917fd2be763f067a58ef05fadcf43efab1.zip | |
OvmfPkg: RiscV64: build BaseRiscVFpuLib
Enable building the BaseRiscVFpuLib library for OvmfPkg to
* Enable the FPU and set it to state 'dirty'.
* Clear the fcsr CSR.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
| -rw-r--r-- | OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc index b521570554..b7ab32f79d 100644 --- a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc +++ b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc @@ -78,6 +78,7 @@ # RISC-V Architectural Libraries
CpuExceptionHandlerLib|UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/BaseRiscV64CpuExceptionHandlerLib.inf
RiscVSbiLib|MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf
+ RiscVFpuLib|UefiCpuPkg/Library/BaseRiscVFpuLib/BaseRiscVFpuLib.inf
RiscVMmuLib|UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
PlatformBootManagerLib|OvmfPkg/RiscVVirt/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
ResetSystemLib|OvmfPkg/RiscVVirt/Library/ResetSystemLib/BaseResetSystemLib.inf
|