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| author | Matt DeVillier <matt.devillier@gmail.com> | 2022-12-16 16:58:05 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2022-12-21 00:46:58 +0000 |
| commit | 01c2fb0d2260d4de898e4e91e48770ffa5510153 (patch) | |
| tree | 3a5f56f6e5914654a858a8fd80318fc0a3148a70 | |
| parent | 3f378450dfafc11754bfdb64af28060ec8466acb (diff) | |
| download | edk2-01c2fb0d2260d4de898e4e91e48770ffa5510153.tar.gz edk2-01c2fb0d2260d4de898e4e91e48770ffa5510153.tar.bz2 edk2-01c2fb0d2260d4de898e4e91e48770ffa5510153.zip | |
MdeModulePkg/XhciDxe/Xhci: Don't check for invalid PSIV
PSID matching relies on comparing the PSIV against the PortSpeed
value. This patch stops edk2 from checking for a PSIV of 0, as it
is not valid; this reduces the number of register access by
approximately 6 per second.
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
| -rw-r--r-- | MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c | 44 |
1 files changed, 25 insertions, 19 deletions
diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c index 15fb49f28f..8dd7a8fbb7 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c +++ b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c @@ -371,6 +371,7 @@ XhcGetRootHubPortStatus ( UINT32 TotalPort;
UINTN Index;
UINTN MapSize;
+ UINT8 PortSpeed;
EFI_STATUS Status;
USB_DEV_ROUTE ParentRouteChart;
EFI_TPL OldTpl;
@@ -397,32 +398,37 @@ XhcGetRootHubPortStatus ( State = XhcReadOpReg (Xhc, Offset);
+ PortSpeed = (State & XHC_PORTSC_PS) >> 10;
+
//
// According to XHCI 1.1 spec November 2017,
// Section 7.2 xHCI Support Protocol Capability
//
- PortStatus->PortStatus = XhcCheckUsbPortSpeedUsedPsic (Xhc, ((State & XHC_PORTSC_PS) >> 10));
- if (PortStatus->PortStatus == 0) {
- //
- // According to XHCI 1.1 spec November 2017,
- // bit 10~13 of the root port status register identifies the speed of the attached device.
- //
- switch ((State & XHC_PORTSC_PS) >> 10) {
- case 2:
- PortStatus->PortStatus |= USB_PORT_STAT_LOW_SPEED;
- break;
+ if (PortSpeed > 0) {
+ PortStatus->PortStatus = XhcCheckUsbPortSpeedUsedPsic (Xhc, PortSpeed);
+ // If no match found in ext cap reg, fall back to PORTSC
+ if (PortStatus->PortStatus == 0) {
+ //
+ // According to XHCI 1.1 spec November 2017,
+ // bit 10~13 of the root port status register identifies the speed of the attached device.
+ //
+ switch (PortSpeed) {
+ case 2:
+ PortStatus->PortStatus |= USB_PORT_STAT_LOW_SPEED;
+ break;
- case 3:
- PortStatus->PortStatus |= USB_PORT_STAT_HIGH_SPEED;
- break;
+ case 3:
+ PortStatus->PortStatus |= USB_PORT_STAT_HIGH_SPEED;
+ break;
- case 4:
- case 5:
- PortStatus->PortStatus |= USB_PORT_STAT_SUPER_SPEED;
- break;
+ case 4:
+ case 5:
+ PortStatus->PortStatus |= USB_PORT_STAT_SUPER_SPEED;
+ break;
- default:
- break;
+ default:
+ break;
+ }
}
}
|