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| author | Zhiguang Liu <zhiguang.liu@intel.com> | 2023-01-04 11:42:43 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2023-02-03 08:24:55 +0000 |
| commit | 13b97736c876919b9786055829caaa4fa46984b7 (patch) | |
| tree | 3c86dc7643fa08d1257187c1ba93905be5f8e275 | |
| parent | 11f0014c0e3046e3762eac420b760091d0cdc063 (diff) | |
| download | edk2-13b97736c876919b9786055829caaa4fa46984b7.tar.gz edk2-13b97736c876919b9786055829caaa4fa46984b7.tar.bz2 edk2-13b97736c876919b9786055829caaa4fa46984b7.zip | |
UefiCpuPkg: Fix SMM code hangs when InitPaging
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4246
In function InitPaging, NumberOfPml5Entries is calculated by below code
NumberOfPml5Entries = (UINTN)LShiftU64 (1, SizeOfMemorySpace - 48);
If the SizeOfMemorySpace is larger than 48, NumberOfPml5Entries will be
larger than 1. However, this doesn't make sense if the hardware doesn't
support 5 level page table.
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Wu, Jiaxin <jiaxin.wu@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Eric Dong <eric.dong@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
| -rw-r--r-- | UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c index c1efda7126..1b0b6673e1 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c @@ -1,7 +1,7 @@ /** @file
Enable SMM profile.
-Copyright (c) 2012 - 2019, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2012 - 2023, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2017 - 2020, AMD Incorporated. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -587,13 +587,18 @@ InitPaging ( }
SizeOfMemorySpace = HighBitSet64 (gPhyMask) + 1;
+ ASSERT (SizeOfMemorySpace <= 52);
+
//
- // Calculate the table entries of PML4E and PDPTE.
+ // Calculate the table entries of PML5E, PML4E and PDPTE.
//
NumberOfPml5Entries = 1;
if (SizeOfMemorySpace > 48) {
- NumberOfPml5Entries = (UINTN)LShiftU64 (1, SizeOfMemorySpace - 48);
- SizeOfMemorySpace = 48;
+ if (Enable5LevelPaging) {
+ NumberOfPml5Entries = (UINTN)LShiftU64 (1, SizeOfMemorySpace - 48);
+ }
+
+ SizeOfMemorySpace = 48;
}
NumberOfPml4Entries = 1;
|