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| author | Ray Ni <ray.ni@intel.com> | 2023-06-15 18:19:51 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2023-06-27 10:16:25 +0000 |
| commit | 8ef7e222ae1f4fdd695a69fcfcfff259147c9502 (patch) | |
| tree | c4e9a0faaa6a820a55b393721117858bc88e39c1 | |
| parent | ab85db32608980d7f1bfc9dc2b4de726373c8ae9 (diff) | |
| download | edk2-8ef7e222ae1f4fdd695a69fcfcfff259147c9502.tar.gz edk2-8ef7e222ae1f4fdd695a69fcfcfff259147c9502.tar.bz2 edk2-8ef7e222ae1f4fdd695a69fcfcfff259147c9502.zip | |
UefiCpuPkg/ResetVector: Add guidance of FDF ffs rule
ResetVector assembly implementation puts "ALIGN 16" in the end
to guarantee the final executable file size is multiple of 16 bytes.
Because the module uses a special GUID which guarantees it's put in
the very end of a FV, which should be also the end of the FD.
All of these (file size is multiple of 16B, and the module is put at
end of FV, FV is put at end of FD) guarantee the "JMP xxx" instruction
is at FFFF_FFF0h.
This patch updates INF file and ReadMe.txt to add guidance of FDF ffs
rule for the ResetVector.
Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
| -rw-r--r-- | UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt | 27 | ||||
| -rw-r--r-- | UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf | 19 |
2 files changed, 25 insertions, 21 deletions
diff --git a/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt b/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt index 97f4600968..4fcb15c3b1 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt +++ b/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt @@ -1,15 +1,16 @@ === HOW TO USE VTF0 ===
+Add this line to your DSC [Components.IA32] or [Components.X64] section:
+ UefiCpuPkg/ResetVector/Vtf0/ResetVector.inf
Add this line to your FDF FV section:
-INF RuleOverride=RESET_VECTOR USE = IA32 UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.inf
-(For X64 SEC/PEI change IA32 to X64 => 'USE = X64')
+ INF RuleOverride=RESET_VECTOR UefiCpuPkg/ResetVector/Vtf0/ResetVector.inf
In your FDF FFS file rules sections add:
-[Rule.Common.SEC.RESET_VECTOR]
- FILE RAW = $(NAMED_GUID) {
- RAW RAW |.raw
- }
+ [Rule.Common.SEC.RESET_VECTOR]
+ FILE RAW = $(NAMED_GUID) {
+ RAW BIN |.bin
+ }
=== VTF0 Boot Flow ===
@@ -25,17 +26,3 @@ All inputs to SEC image are register based: EAX/RAX - Initial value of the EAX register (BIST: Built-in Self Test)
DI - 'BP': boot-strap processor, or 'AP': application processor
EBP/RBP - Pointer to the start of the Boot Firmware Volume
-
-=== HOW TO BUILD VTF0 ===
-
-Dependencies:
-* Python 3 or newer
-* Nasm 2.03 or newer
-
-To rebuild the VTF0 binaries:
-1. Change to VTF0 source dir: UefiCpuPkg/ResetVector/Vtf0
-2. nasm and python should be in executable path
-3. Run this command:
- python Build.py
-4. Binaries output will be in UefiCpuPkg/ResetVector/Vtf0/Bin
-
diff --git a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf index 9922cb2755..03d92d937f 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf +++ b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf @@ -1,7 +1,24 @@ ## @file
# Reset Vector
#
-# Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
+# Note:
+# Conf/build_rule.txt contains the build rule [Nasm-to-Binary-Code-File]
+# to generate .bin file from .nasmb source.
+#
+# The platform FDF MUST have a FDF rule as follows to build the .bin
+# file as ResetVector .ffs file:
+#
+# [Rule.Common.SEC.RESET_VECTOR]
+# FILE RAW = $(NAMED_GUID) {
+# RAW BIN |.bin
+# }
+#
+# Following line in FDF forces to use the above rule for the ResetVector:
+#
+# INF RuleOverride=RESET_VECTOR UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf
+#
+#
+# Copyright (c) 2006 - 2023, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
|