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authorRanbir Singh <Ranbir.Singh3@Dell.com>2023-08-16 13:38:02 +0800
committermergify[bot] <37929162+mergify[bot]@users.noreply.github.com>2023-09-22 04:56:35 +0000
commite9f5d8c0e066da55b3f79dfdbf4df5fc97ca5916 (patch)
tree6f364c8809961e8320f7b01cdc92944f18504a00
parentf67e1934d985dcb8a465dcf44484be3688be99a5 (diff)
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MdeModulePkg/Bus/Pci/UhciDxe: Fix BAD_SHIFT Coverity issue
The function UhciConvertPollRate has a check ASSERT (Interval != 0); but this comes into play only in DEBUG mode. In Release mode, there is no handling if the Interval parameter value is ZERO. To avoid shifting by a negative amount later in the code flow in this undesirable case, it is better to handle it as well by treating it same as if 1 is sent. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4211 Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Co-authored-by: Veeresh Sangolli <veeresh.sangolli@dellteam.com> Signed-off-by: Ranbir Singh <Ranbir.Singh3@Dell.com> Signed-off-by: Ranbir Singh <rsingh@ventanamicro.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
-rw-r--r--MdeModulePkg/Bus/Pci/UhciDxe/UhciSched.c10
1 files changed, 9 insertions, 1 deletions
diff --git a/MdeModulePkg/Bus/Pci/UhciDxe/UhciSched.c b/MdeModulePkg/Bus/Pci/UhciDxe/UhciSched.c
index c08f949696..408e7d5ab7 100644
--- a/MdeModulePkg/Bus/Pci/UhciDxe/UhciSched.c
+++ b/MdeModulePkg/Bus/Pci/UhciDxe/UhciSched.c
@@ -197,7 +197,7 @@ UhciDestoryFrameList (
}
/**
- Convert the poll rate to the maxium 2^n that is smaller
+ Convert the poll rate to the maximum 2^n that is smaller
than Interval.
@param Interval The poll rate to convert.
@@ -215,6 +215,14 @@ UhciConvertPollRate (
ASSERT (Interval != 0);
//
+ // To safeguard RELEASE mode wherein ASSERT is effectively not there,
+ // if inadvertently Interval is still 0 here, treat it the same as 1.
+ //
+ if (Interval == 0) {
+ Interval = 1;
+ }
+
+ //
// Find the index (1 based) of the highest non-zero bit
//
BitCount = 0;