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| author | Tuan Phan <tphan@ventanamicro.com> | 2023-10-04 11:34:26 -0700 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2023-10-17 07:44:25 +0000 |
| commit | 772ec92577a8c786b6c9f8643fa60f1cf893bcd9 (patch) | |
| tree | cd9abd9ed7455fdb29587910e5aa938aadf7e45d | |
| parent | a445e1a42ccf3cb9f70537c7cd80ece689bf4d9a (diff) | |
| download | edk2-772ec92577a8c786b6c9f8643fa60f1cf893bcd9.tar.gz edk2-772ec92577a8c786b6c9f8643fa60f1cf893bcd9.tar.bz2 edk2-772ec92577a8c786b6c9f8643fa60f1cf893bcd9.zip | |
UefiCpuPkg: RISC-V: MMU: Introduce a PCD for SATP mode
Introduce a PCD to control the maximum SATP mode that MMU allowed
to use. This PCD helps RISC-V platform set bare or minimum SATP mode
during bring up to debug memory map issue.
Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
Reviewed-by: Dhaval Sharma <dhaval@rivosinc.com>
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
| -rw-r--r-- | UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 6 | ||||
| -rw-r--r-- | UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 3 | ||||
| -rw-r--r-- | UefiCpuPkg/UefiCpuPkg.dec | 8 |
3 files changed, 16 insertions, 1 deletions
diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c index 9cca5fc128..826a1d32a1 100644 --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c @@ -36,7 +36,7 @@ #define PTE_PPN_SHIFT 10
#define RISCV_MMU_PAGE_SHIFT 12
-STATIC UINTN mModeSupport[] = { SATP_MODE_SV57, SATP_MODE_SV48, SATP_MODE_SV39 };
+STATIC UINTN mModeSupport[] = { SATP_MODE_SV57, SATP_MODE_SV48, SATP_MODE_SV39, SATP_MODE_OFF };
STATIC UINTN mMaxRootTableLevel;
STATIC UINTN mBitPerLevel;
STATIC UINTN mTableEntryCount;
@@ -590,6 +590,10 @@ RiscVMmuSetSatpMode ( UINTN Index;
EFI_STATUS Status;
+ if (SatpMode > PcdGet32 (PcdCpuRiscVMmuMaxSatpMode)) {
+ return EFI_DEVICE_ERROR;
+ }
+
switch (SatpMode) {
case SATP_MODE_OFF:
return EFI_SUCCESS;
diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf index 9b28a98cb3..51ebe1750e 100644 --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf @@ -25,3 +25,6 @@ [LibraryClasses]
BaseLib
+
+[Pcd]
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode ## CONSUMES
diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec index 68473fc640..0b5431dbf7 100644 --- a/UefiCpuPkg/UefiCpuPkg.dec +++ b/UefiCpuPkg/UefiCpuPkg.dec @@ -396,6 +396,14 @@ # @Prompt Access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|TRUE|BOOLEAN|0x3213210F
+[PcdsFixedAtBuild.RISCV64]
+ ## Indicate the maximum SATP mode allowed.
+ # 0 - Bare mode.
+ # 8 - 39bit mode.
+ # 9 - 48bit mode.
+ # 10 - 57bit mode.
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode|10|UINT32|0x60000021
+
[PcdsDynamic, PcdsDynamicEx]
## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DATA.
# @Prompt The pointer to a CPU S3 data buffer.
|