diff options
| author | Dhaval Sharma <dhaval@rivosinc.com> | 2023-12-13 20:29:27 +0530 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2023-12-19 12:48:14 +0000 |
| commit | 286b30f517ef35ae2764f13f077f0f120372a286 (patch) | |
| tree | 5a57ffbc9fe0718717aa64aea5682d14af3b359d | |
| parent | 3c66390e4a514dcce4c8cc82f489d653d55ee3fa (diff) | |
| download | edk2-286b30f517ef35ae2764f13f077f0f120372a286.tar.gz edk2-286b30f517ef35ae2764f13f077f0f120372a286.tar.bz2 edk2-286b30f517ef35ae2764f13f077f0f120372a286.zip | |
MdePkg: Move RISC-V Cache Management Declarations Into BaseLib
The declarations for cache Management functions belong to BaseLib
instead of instance source file. This helps with further restructuring
of cache management code for RISC-V.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Pedro Falcato <pedro.falcato@gmail.com>
Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
| -rw-r--r-- | MdePkg/Include/Library/BaseLib.h | 20 | ||||
| -rw-r--r-- | MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 20 |
2 files changed, 20 insertions, 20 deletions
diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h index 728e89d2bf..2c69c5f528 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -206,6 +206,26 @@ RiscVClearPendingTimerInterrupt ( VOID
);
+/**
+ RISC-V invalidate instruction cache.
+
+**/
+VOID
+EFIAPI
+RiscVInvalidateInstCacheAsm (
+ VOID
+ );
+
+/**
+ RISC-V invalidate data cache.
+
+**/
+VOID
+EFIAPI
+RiscVInvalidateDataCacheAsm (
+ VOID
+ );
+
#endif // defined (MDE_CPU_RISCV64)
#if defined (MDE_CPU_LOONGARCH64)
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c index d08fb9f193..d5efcf49a4 100644 --- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c +++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c @@ -11,26 +11,6 @@ #include <Library/DebugLib.h>
/**
- RISC-V invalidate instruction cache.
-
-**/
-VOID
-EFIAPI
-RiscVInvalidateInstCacheAsm (
- VOID
- );
-
-/**
- RISC-V invalidate data cache.
-
-**/
-VOID
-EFIAPI
-RiscVInvalidateDataCacheAsm (
- VOID
- );
-
-/**
Invalidates the entire instruction cache in cache coherency domain of the
calling CPU.
|