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authorStar Zeng <star.zeng@intel.com>2017-08-02 10:07:31 +0800
committerStar Zeng <star.zeng@intel.com>2017-08-02 18:21:54 +0800
commit59d3fad32ec928d91be3d6fbc3a5aab3409b5f68 (patch)
tree873ca3e5c9bef5f04cc1d98435944231b8bb02a9
parent354a75f9ed0d2f37ace0614135e08e6a8b83e174 (diff)
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UefiCpuPkg SecCore: Fix operands of different size in bitwise operation
It is introduced by 9e9ca2100f22be29f1a53129d741f4305ff34a71. Cc: Hao Wu <hao.a.wu@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
-rw-r--r--UefiCpuPkg/SecCore/SecMain.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/UefiCpuPkg/SecCore/SecMain.c b/UefiCpuPkg/SecCore/SecMain.c
index e9e243ca05..173bbfcfcb 100644
--- a/UefiCpuPkg/SecCore/SecMain.c
+++ b/UefiCpuPkg/SecCore/SecMain.c
@@ -281,7 +281,7 @@ SecStartupPhase2(
// will be built based on them in PEI phase.
//
SecCoreData->PeiTemporaryRamBase = (VOID *)(((UINTN)SecCoreData->PeiTemporaryRamBase + 7) & ~0x07);
- SecCoreData->PeiTemporaryRamSize &= ~0x07;
+ SecCoreData->PeiTemporaryRamSize &= ~(UINTN)0x07;
} else {
//
// No addition PPI, PpiList directly point to the common PPI list.