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| author | Laszlo Ersek <lersek@redhat.com> | 2019-05-29 11:52:03 +0200 |
|---|---|---|
| committer | Laszlo Ersek <lersek@redhat.com> | 2019-06-03 19:54:15 +0200 |
| commit | d4534984111328ff839fbf51be2779a98bfefa30 (patch) | |
| tree | 9195cdd19cd9f1023986ec55201fedcf9cca51c1 | |
| parent | 753d3d6f43b2c2bf2df67038608496663ff6e3aa (diff) | |
| download | edk2-d4534984111328ff839fbf51be2779a98bfefa30.tar.gz edk2-d4534984111328ff839fbf51be2779a98bfefa30.tar.bz2 edk2-d4534984111328ff839fbf51be2779a98bfefa30.zip | |
Revert "OvmfPkg/PlatformPei: assign PciSize on both i440fx/q35 branches explicitly"
This reverts commit 60e95bf5094fbb9b728729ccfaf32184b3662317.
The original fix for <https://bugzilla.tianocore.org/show_bug.cgi?id=1814>
triggered a bug / incorrect assumption in QEMU.
QEMU assumes that the PCIEXBAR is below the 32-bit PCI window, not above
it. When the firmware doesn't satisfy this assumption, QEMU generates an
\_SB.PCI0._CRS object in the ACPI DSDT that does not reflect the
firmware's 32-bit MMIO BAR assignments. This causes OSes to re-assign
32-bit MMIO BARs.
Working around the problem in the firmware looks less problematic than
fixing QEMU. Revert the original changes first, before implementing an
alternative fix.
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1859
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com>
| -rw-r--r-- | OvmfPkg/PlatformPei/Platform.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index 5e0a154842..0876316eef 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -190,10 +190,8 @@ MemMapInitialization ( ASSERT (TopOfLowRam <= PciExBarBase);
ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);
PciBase = (UINT32)(PciExBarBase + SIZE_256MB);
- PciSize = 0xFC000000 - PciBase;
} else {
PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;
- PciSize = 0xFC000000 - PciBase;
}
//
@@ -209,6 +207,7 @@ MemMapInitialization ( // 0xFED20000 gap 896 KB
// 0xFEE00000 LAPIC 1 MB
//
+ PciSize = 0xFC000000 - PciBase;
AddIoMemoryBaseSizeHob (PciBase, PciSize);
PcdStatus = PcdSet64S (PcdPciMmio32Base, PciBase);
ASSERT_RETURN_ERROR (PcdStatus);
|