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| author | Ray Ni <ray.ni@intel.com> | 2022-07-15 15:22:57 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2022-08-09 07:08:05 +0000 |
| commit | c16f02f7764cba228d9c70b7985ff7276b6de4cc (patch) | |
| tree | 88f887979465352628dc5d26bd12eeb3037be5be | |
| parent | 9cb8974f06c6cc2545a66e696a58911122dec9fd (diff) | |
| download | edk2-c16f02f7764cba228d9c70b7985ff7276b6de4cc.tar.gz edk2-c16f02f7764cba228d9c70b7985ff7276b6de4cc.tar.bz2 edk2-c16f02f7764cba228d9c70b7985ff7276b6de4cc.zip | |
CpuPageTableLib: Avoid treating non-leaf entry as leaf one
Today's logic wrongly treats the non-leaf entry as leaf entry and
updates its paging attributes.
The patch fixes the bug to only update paging attributes for
non-present entries or leaf entries.
Signed-off-by: Ray Ni <ray.ni@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
| -rw-r--r-- | UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c index d02fd5efa2..0df744cb9b 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -248,6 +248,7 @@ PageTableLibMapInLevel ( UINTN BitStart;
UINTN Index;
IA32_PAGING_ENTRY *PagingEntry;
+ IA32_PAGING_ENTRY *CurrentPagingEntry;
UINT64 RegionLength;
UINT64 SubLength;
UINT64 SubOffset;
@@ -359,18 +360,20 @@ PageTableLibMapInLevel ( //
PagingEntry = (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE_BASE_ADDRESS (&ParentPagingEntry->Pnle);
while (Offset < Length && Index < 512) {
- SubLength = MIN (Length - Offset, RegionStart + RegionLength - (LinearAddress + Offset));
+ CurrentPagingEntry = (!Modify && CreateNew) ? &OneOfPagingEntry : &PagingEntry[Index];
+ SubLength = MIN (Length - Offset, RegionStart + RegionLength - (LinearAddress + Offset));
if ((Level <= MaxLeafLevel) &&
(((LinearAddress + Offset) & RegionMask) == 0) &&
(((IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (Attribute) + Offset) & RegionMask) == 0) &&
- (SubLength == RegionLength)
+ (SubLength == RegionLength) &&
+ ((CurrentPagingEntry->Pce.Present == 0) || IsPle (CurrentPagingEntry, Level))
)
{
//
// Create one entry mapping the entire region (1G, 2M or 4K).
//
if (Modify) {
- PageTableLibSetPle (Level, &PagingEntry[Index], Offset, Attribute, Mask);
+ PageTableLibSetPle (Level, CurrentPagingEntry, Offset, Attribute, Mask);
}
} else {
//
@@ -382,7 +385,7 @@ PageTableLibMapInLevel ( // but the length is SMALLER than the RegionLength.
//
Status = PageTableLibMapInLevel (
- (!Modify && CreateNew) ? &OneOfPagingEntry : &PagingEntry[Index],
+ CurrentPagingEntry,
Modify,
Buffer,
BufferSize,
|