UefiCpuPkg: Simplify the struct definition of CPU_EXCEPTION_INIT_DATA

CPU_EXCEPTION_INIT_DATA is now an internal implementation of
CpuExceptionHandlerLib. Union can be removed since Ia32 and X64 have the
same definition. Also, two fields (Revision and InitDefaultHandlers)are
useless, can be removed.

Cc: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>

5 files changed, 145 insertions, 161 deletions

diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
index 443eaf359b..11a5624f51 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
@@ -49,71 +49,59 @@
 

 #define CPU_TSS_GDT_SIZE  (SIZE_2KB + CPU_TSS_DESC_SIZE + CPU_TSS_SIZE)

 

-#define CPU_EXCEPTION_INIT_DATA_REV  1

-

-typedef union {

-  struct {

-    //

-    // Revision number of this structure.

-    //

-    UINT32     Revision;

-    //

-    // The address of top of known good stack reserved for *ALL* exceptions

-    // listed in field StackSwitchExceptions.

-    //

-    UINTN      KnownGoodStackTop;

-    //

-    // The size of known good stack for *ONE* exception only.

-    //

-    UINTN      KnownGoodStackSize;

-    //

-    // Buffer of exception vector list for stack switch.

-    //

-    UINT8      *StackSwitchExceptions;

-    //

-    // Number of exception vectors in StackSwitchExceptions.

-    //

-    UINTN      StackSwitchExceptionNumber;

-    //

-    // Buffer of IDT table. It must be type of IA32_IDT_GATE_DESCRIPTOR.

-    // Normally there's no need to change IDT table size.

-    //

-    VOID       *IdtTable;

-    //

-    // Size of buffer for IdtTable.

-    //

-    UINTN      IdtTableSize;

-    //

-    // Buffer of GDT table. It must be type of IA32_SEGMENT_DESCRIPTOR.

-    //

-    VOID       *GdtTable;

-    //

-    // Size of buffer for GdtTable.

-    //

-    UINTN      GdtTableSize;

-    //

-    // Pointer to start address of descriptor of exception task gate in the

-    // GDT table. It must be type of IA32_TSS_DESCRIPTOR.

-    //

-    VOID       *ExceptionTssDesc;

-    //

-    // Size of buffer for ExceptionTssDesc.

-    //

-    UINTN      ExceptionTssDescSize;

-    //

-    // Buffer of task-state segment for exceptions. It must be type of

-    // IA32_TASK_STATE_SEGMENT.

-    //

-    VOID       *ExceptionTss;

-    //

-    // Size of buffer for ExceptionTss.

-    //

-    UINTN      ExceptionTssSize;

-    //

-    // Flag to indicate if default handlers should be initialized or not.

-    //

-    BOOLEAN    InitDefaultHandlers;

-  } Ia32, X64;

+typedef struct {

+  //

+  // The address of top of known good stack reserved for *ALL* exceptions

+  // listed in field StackSwitchExceptions.

+  //

+  UINTN    KnownGoodStackTop;

+  //

+  // The size of known good stack for *ONE* exception only.

+  //

+  UINTN    KnownGoodStackSize;

+  //

+  // Buffer of exception vector list for stack switch.

+  //

+  UINT8    *StackSwitchExceptions;

+  //

+  // Number of exception vectors in StackSwitchExceptions.

+  //

+  UINTN    StackSwitchExceptionNumber;

+  //

+  // Buffer of IDT table. It must be type of IA32_IDT_GATE_DESCRIPTOR.

+  // Normally there's no need to change IDT table size.

+  //

+  VOID     *IdtTable;

+  //

+  // Size of buffer for IdtTable.

+  //

+  UINTN    IdtTableSize;

+  //

+  // Buffer of GDT table. It must be type of IA32_SEGMENT_DESCRIPTOR.

+  //

+  VOID     *GdtTable;

+  //

+  // Size of buffer for GdtTable.

+  //

+  UINTN    GdtTableSize;

+  //

+  // Pointer to start address of descriptor of exception task gate in the

+  // GDT table. It must be type of IA32_TSS_DESCRIPTOR.

+  //

+  VOID     *ExceptionTssDesc;

+  //

+  // Size of buffer for ExceptionTssDesc.

+  //

+  UINTN    ExceptionTssDescSize;

+  //

+  // Buffer of task-state segment for exceptions. It must be type of

+  // IA32_TASK_STATE_SEGMENT.

+  //

+  VOID     *ExceptionTss;

+  //

+  // Size of buffer for ExceptionTss.

+  //

+  UINTN    ExceptionTssSize;

 } CPU_EXCEPTION_INIT_DATA;

 

 //

diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
index 04e8409922..d90c607bd7 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
@@ -190,19 +190,18 @@ InitializeSeparateExceptionStacks (
   }

 

   AsmReadIdtr (&Idtr);

-  EssData.X64.Revision                   = CPU_EXCEPTION_INIT_DATA_REV;

-  EssData.X64.KnownGoodStackTop          = StackTop;

-  EssData.X64.KnownGoodStackSize         = CPU_KNOWN_GOOD_STACK_SIZE;

-  EssData.X64.StackSwitchExceptions      = CPU_STACK_SWITCH_EXCEPTION_LIST;

-  EssData.X64.StackSwitchExceptionNumber = CPU_STACK_SWITCH_EXCEPTION_NUMBER;

-  EssData.X64.IdtTable                   = (VOID *)Idtr.Base;

-  EssData.X64.IdtTableSize               = Idtr.Limit + 1;

-  EssData.X64.GdtTable                   = NewGdtTable;

-  EssData.X64.GdtTableSize               = CPU_TSS_DESC_SIZE + Gdtr.Limit + 1;

-  EssData.X64.ExceptionTssDesc           = NewGdtTable + Gdtr.Limit + 1;

-  EssData.X64.ExceptionTssDescSize       = CPU_TSS_DESC_SIZE;

-  EssData.X64.ExceptionTss               = NewGdtTable + Gdtr.Limit + 1 + CPU_TSS_DESC_SIZE;

-  EssData.X64.ExceptionTssSize           = CPU_TSS_SIZE;

+  EssData.KnownGoodStackTop          = StackTop;

+  EssData.KnownGoodStackSize         = CPU_KNOWN_GOOD_STACK_SIZE;

+  EssData.StackSwitchExceptions      = CPU_STACK_SWITCH_EXCEPTION_LIST;

+  EssData.StackSwitchExceptionNumber = CPU_STACK_SWITCH_EXCEPTION_NUMBER;

+  EssData.IdtTable                   = (VOID *)Idtr.Base;

+  EssData.IdtTableSize               = Idtr.Limit + 1;

+  EssData.GdtTable                   = NewGdtTable;

+  EssData.GdtTableSize               = CPU_TSS_DESC_SIZE + Gdtr.Limit + 1;

+  EssData.ExceptionTssDesc           = NewGdtTable + Gdtr.Limit + 1;

+  EssData.ExceptionTssDescSize       = CPU_TSS_DESC_SIZE;

+  EssData.ExceptionTss               = NewGdtTable + Gdtr.Limit + 1 + CPU_TSS_DESC_SIZE;

+  EssData.ExceptionTssSize           = CPU_TSS_SIZE;

 

   return ArchSetupExceptionStack (&EssData);

 }

diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
index f13e8e7020..194d3a499b 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
@@ -1,7 +1,7 @@
 /** @file

   IA32 CPU Exception Handler functons.

 

-  Copyright (c) 2012 - 2019, Intel Corporation. All rights reserved.<BR>

+  Copyright (c) 2012 - 2022, Intel Corporation. All rights reserved.<BR>

   SPDX-License-Identifier: BSD-2-Clause-Patent

 

 **/

@@ -132,16 +132,15 @@ ArchSetupExceptionStack (
   EXCEPTION_HANDLER_TEMPLATE_MAP  TemplateMap;

 

   if ((StackSwitchData == NULL) ||

-      (StackSwitchData->Ia32.Revision != CPU_EXCEPTION_INIT_DATA_REV) ||

-      (StackSwitchData->Ia32.KnownGoodStackTop == 0) ||

-      (StackSwitchData->Ia32.KnownGoodStackSize == 0) ||

-      (StackSwitchData->Ia32.StackSwitchExceptions == NULL) ||

-      (StackSwitchData->Ia32.StackSwitchExceptionNumber == 0) ||

-      (StackSwitchData->Ia32.StackSwitchExceptionNumber > CPU_EXCEPTION_NUM) ||

-      (StackSwitchData->Ia32.GdtTable == NULL) ||

-      (StackSwitchData->Ia32.IdtTable == NULL) ||

-      (StackSwitchData->Ia32.ExceptionTssDesc == NULL) ||

-      (StackSwitchData->Ia32.ExceptionTss == NULL))

+      (StackSwitchData->KnownGoodStackTop == 0) ||

+      (StackSwitchData->KnownGoodStackSize == 0) ||

+      (StackSwitchData->StackSwitchExceptions == NULL) ||

+      (StackSwitchData->StackSwitchExceptionNumber == 0) ||

+      (StackSwitchData->StackSwitchExceptionNumber > CPU_EXCEPTION_NUM) ||

+      (StackSwitchData->GdtTable == NULL) ||

+      (StackSwitchData->IdtTable == NULL) ||

+      (StackSwitchData->ExceptionTssDesc == NULL) ||

+      (StackSwitchData->ExceptionTss == NULL))

   {

     return EFI_INVALID_PARAMETER;

   }

@@ -151,16 +150,16 @@ ArchSetupExceptionStack (
   // one or newly allocated, has enough space to hold descriptors for exception

   // task-state segments.

   //

-  if (((UINTN)StackSwitchData->Ia32.GdtTable & (IA32_GDT_ALIGNMENT - 1)) != 0) {

+  if (((UINTN)StackSwitchData->GdtTable & (IA32_GDT_ALIGNMENT - 1)) != 0) {

     return EFI_INVALID_PARAMETER;

   }

 

-  if ((UINTN)StackSwitchData->Ia32.ExceptionTssDesc < (UINTN)(StackSwitchData->Ia32.GdtTable)) {

+  if ((UINTN)StackSwitchData->ExceptionTssDesc < (UINTN)(StackSwitchData->GdtTable)) {

     return EFI_INVALID_PARAMETER;

   }

 

-  if ((UINTN)StackSwitchData->Ia32.ExceptionTssDesc + StackSwitchData->Ia32.ExceptionTssDescSize >

-      ((UINTN)(StackSwitchData->Ia32.GdtTable) + StackSwitchData->Ia32.GdtTableSize))

+  if ((UINTN)StackSwitchData->ExceptionTssDesc + StackSwitchData->ExceptionTssDescSize >

+      ((UINTN)(StackSwitchData->GdtTable) + StackSwitchData->GdtTableSize))

   {

     return EFI_INVALID_PARAMETER;

   }

@@ -169,20 +168,20 @@ ArchSetupExceptionStack (
   // We need one descriptor and one TSS for current task and every exception

   // specified.

   //

-  if (StackSwitchData->Ia32.ExceptionTssDescSize <

-      sizeof (IA32_TSS_DESCRIPTOR) * (StackSwitchData->Ia32.StackSwitchExceptionNumber + 1))

+  if (StackSwitchData->ExceptionTssDescSize <

+      sizeof (IA32_TSS_DESCRIPTOR) * (StackSwitchData->StackSwitchExceptionNumber + 1))

   {

     return EFI_INVALID_PARAMETER;

   }

 

-  if (StackSwitchData->Ia32.ExceptionTssSize <

-      sizeof (IA32_TASK_STATE_SEGMENT) * (StackSwitchData->Ia32.StackSwitchExceptionNumber + 1))

+  if (StackSwitchData->ExceptionTssSize <

+      sizeof (IA32_TASK_STATE_SEGMENT) * (StackSwitchData->StackSwitchExceptionNumber + 1))

   {

     return EFI_INVALID_PARAMETER;

   }

 

-  TssDesc = StackSwitchData->Ia32.ExceptionTssDesc;

-  Tss     = StackSwitchData->Ia32.ExceptionTss;

+  TssDesc = StackSwitchData->ExceptionTssDesc;

+  Tss     = StackSwitchData->ExceptionTss;

 

   //

   // Initialize new GDT table and/or IDT table, if any

@@ -192,20 +191,20 @@ ArchSetupExceptionStack (
 

   GdtSize = (UINTN)TssDesc +

             sizeof (IA32_TSS_DESCRIPTOR) *

-            (StackSwitchData->Ia32.StackSwitchExceptionNumber + 1) -

-            (UINTN)(StackSwitchData->Ia32.GdtTable);

-  if ((UINTN)StackSwitchData->Ia32.GdtTable != Gdtr.Base) {

-    CopyMem (StackSwitchData->Ia32.GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit + 1);

-    Gdtr.Base  = (UINTN)StackSwitchData->Ia32.GdtTable;

+            (StackSwitchData->StackSwitchExceptionNumber + 1) -

+            (UINTN)(StackSwitchData->GdtTable);

+  if ((UINTN)StackSwitchData->GdtTable != Gdtr.Base) {

+    CopyMem (StackSwitchData->GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit + 1);

+    Gdtr.Base  = (UINTN)StackSwitchData->GdtTable;

     Gdtr.Limit = (UINT16)GdtSize - 1;

   }

 

-  if ((UINTN)StackSwitchData->Ia32.IdtTable != Idtr.Base) {

-    Idtr.Base = (UINTN)StackSwitchData->Ia32.IdtTable;

+  if ((UINTN)StackSwitchData->IdtTable != Idtr.Base) {

+    Idtr.Base = (UINTN)StackSwitchData->IdtTable;

   }

 

-  if (StackSwitchData->Ia32.IdtTableSize > 0) {

-    Idtr.Limit = (UINT16)(StackSwitchData->Ia32.IdtTableSize - 1);

+  if (StackSwitchData->IdtTableSize > 0) {

+    Idtr.Limit = (UINT16)(StackSwitchData->IdtTableSize - 1);

   }

 

   //

@@ -227,10 +226,10 @@ ArchSetupExceptionStack (
   // Fixup exception task descriptor and task-state segment

   //

   AsmGetTssTemplateMap (&TemplateMap);

-  StackTop = StackSwitchData->Ia32.KnownGoodStackTop - CPU_STACK_ALIGNMENT;

+  StackTop = StackSwitchData->KnownGoodStackTop - CPU_STACK_ALIGNMENT;

   StackTop = (UINTN)ALIGN_POINTER (StackTop, CPU_STACK_ALIGNMENT);

-  IdtTable = StackSwitchData->Ia32.IdtTable;

-  for (Index = 0; Index < StackSwitchData->Ia32.StackSwitchExceptionNumber; ++Index) {

+  IdtTable = StackSwitchData->IdtTable;

+  for (Index = 0; Index < StackSwitchData->StackSwitchExceptionNumber; ++Index) {

     TssDesc += 1;

     Tss     += 1;

 

@@ -251,7 +250,7 @@ ArchSetupExceptionStack (
     //

     // Fixup TSS

     //

-    Vector = StackSwitchData->Ia32.StackSwitchExceptions[Index];

+    Vector = StackSwitchData->StackSwitchExceptions[Index];

     if ((Vector >= CPU_EXCEPTION_NUM) ||

         (Vector >= (Idtr.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR)))

     {

@@ -271,7 +270,7 @@ ArchSetupExceptionStack (
     Tss->FS     = AsmReadFs ();

     Tss->GS     = AsmReadGs ();

 

-    StackTop -= StackSwitchData->Ia32.KnownGoodStackSize;

+    StackTop -= StackSwitchData->KnownGoodStackSize;

 

     //

     // Update IDT to use Task Gate for given exception

@@ -291,7 +290,7 @@ ArchSetupExceptionStack (
   //

   // Load current task

   //

-  AsmWriteTr ((UINT16)((UINTN)StackSwitchData->Ia32.ExceptionTssDesc - Gdtr.Base));

+  AsmWriteTr ((UINT16)((UINTN)StackSwitchData->ExceptionTssDesc - Gdtr.Base));

 

   //

   // Publish IDT

diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c
index 52ec0fb803..5952295126 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c
@@ -236,19 +236,18 @@ InitializeSeparateExceptionStacks (
   NewGdtTable = ALIGN_POINTER (StackTop, sizeof (IA32_TSS_DESCRIPTOR));

 

   AsmReadIdtr (&Idtr);

-  EssData.X64.Revision                   = CPU_EXCEPTION_INIT_DATA_REV;

-  EssData.X64.KnownGoodStackTop          = StackTop;

-  EssData.X64.KnownGoodStackSize         = CPU_KNOWN_GOOD_STACK_SIZE;

-  EssData.X64.StackSwitchExceptions      = CPU_STACK_SWITCH_EXCEPTION_LIST;

-  EssData.X64.StackSwitchExceptionNumber = CPU_STACK_SWITCH_EXCEPTION_NUMBER;

-  EssData.X64.IdtTable                   = (VOID *)Idtr.Base;

-  EssData.X64.IdtTableSize               = Idtr.Limit + 1;

-  EssData.X64.GdtTable                   = NewGdtTable;

-  EssData.X64.GdtTableSize               = CPU_TSS_DESC_SIZE + Gdtr.Limit + 1;

-  EssData.X64.ExceptionTssDesc           = NewGdtTable + Gdtr.Limit + 1;

-  EssData.X64.ExceptionTssDescSize       = CPU_TSS_DESC_SIZE;

-  EssData.X64.ExceptionTss               = NewGdtTable + Gdtr.Limit + 1 + CPU_TSS_DESC_SIZE;

-  EssData.X64.ExceptionTssSize           = CPU_TSS_SIZE;

+  EssData.KnownGoodStackTop          = StackTop;

+  EssData.KnownGoodStackSize         = CPU_KNOWN_GOOD_STACK_SIZE;

+  EssData.StackSwitchExceptions      = CPU_STACK_SWITCH_EXCEPTION_LIST;

+  EssData.StackSwitchExceptionNumber = CPU_STACK_SWITCH_EXCEPTION_NUMBER;

+  EssData.IdtTable                   = (VOID *)Idtr.Base;

+  EssData.IdtTableSize               = Idtr.Limit + 1;

+  EssData.GdtTable                   = NewGdtTable;

+  EssData.GdtTableSize               = CPU_TSS_DESC_SIZE + Gdtr.Limit + 1;

+  EssData.ExceptionTssDesc           = NewGdtTable + Gdtr.Limit + 1;

+  EssData.ExceptionTssDescSize       = CPU_TSS_DESC_SIZE;

+  EssData.ExceptionTss               = NewGdtTable + Gdtr.Limit + 1 + CPU_TSS_DESC_SIZE;

+  EssData.ExceptionTssSize           = CPU_TSS_SIZE;

 

   return ArchSetupExceptionStack (&EssData);

 }

diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
index cd7dccd481..c14ac66c43 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
@@ -1,7 +1,7 @@
 /** @file

   x64 CPU Exception Handler.

 

-  Copyright (c) 2012 - 2019, Intel Corporation. All rights reserved.<BR>

+  Copyright (c) 2012 - 2022, Intel Corporation. All rights reserved.<BR>

   SPDX-License-Identifier: BSD-2-Clause-Patent

 

 **/

@@ -136,16 +136,15 @@ ArchSetupExceptionStack (
   UINTN                     GdtSize;

 

   if ((StackSwitchData == NULL) ||

-      (StackSwitchData->Ia32.Revision != CPU_EXCEPTION_INIT_DATA_REV) ||

-      (StackSwitchData->X64.KnownGoodStackTop == 0) ||

-      (StackSwitchData->X64.KnownGoodStackSize == 0) ||

-      (StackSwitchData->X64.StackSwitchExceptions == NULL) ||

-      (StackSwitchData->X64.StackSwitchExceptionNumber == 0) ||

-      (StackSwitchData->X64.StackSwitchExceptionNumber > CPU_EXCEPTION_NUM) ||

-      (StackSwitchData->X64.GdtTable == NULL) ||

-      (StackSwitchData->X64.IdtTable == NULL) ||

-      (StackSwitchData->X64.ExceptionTssDesc == NULL) ||

-      (StackSwitchData->X64.ExceptionTss == NULL))

+      (StackSwitchData->KnownGoodStackTop == 0) ||

+      (StackSwitchData->KnownGoodStackSize == 0) ||

+      (StackSwitchData->StackSwitchExceptions == NULL) ||

+      (StackSwitchData->StackSwitchExceptionNumber == 0) ||

+      (StackSwitchData->StackSwitchExceptionNumber > CPU_EXCEPTION_NUM) ||

+      (StackSwitchData->GdtTable == NULL) ||

+      (StackSwitchData->IdtTable == NULL) ||

+      (StackSwitchData->ExceptionTssDesc == NULL) ||

+      (StackSwitchData->ExceptionTss == NULL))

   {

     return EFI_INVALID_PARAMETER;

   }

@@ -155,16 +154,16 @@ ArchSetupExceptionStack (
   // one or newly allocated, has enough space to hold descriptors for exception

   // task-state segments.

   //

-  if (((UINTN)StackSwitchData->X64.GdtTable & (IA32_GDT_ALIGNMENT - 1)) != 0) {

+  if (((UINTN)StackSwitchData->GdtTable & (IA32_GDT_ALIGNMENT - 1)) != 0) {

     return EFI_INVALID_PARAMETER;

   }

 

-  if ((UINTN)StackSwitchData->X64.ExceptionTssDesc < (UINTN)(StackSwitchData->X64.GdtTable)) {

+  if ((UINTN)StackSwitchData->ExceptionTssDesc < (UINTN)(StackSwitchData->GdtTable)) {

     return EFI_INVALID_PARAMETER;

   }

 

-  if (((UINTN)StackSwitchData->X64.ExceptionTssDesc + StackSwitchData->X64.ExceptionTssDescSize) >

-      ((UINTN)(StackSwitchData->X64.GdtTable) + StackSwitchData->X64.GdtTableSize))

+  if (((UINTN)StackSwitchData->ExceptionTssDesc + StackSwitchData->ExceptionTssDescSize) >

+      ((UINTN)(StackSwitchData->GdtTable) + StackSwitchData->GdtTableSize))

   {

     return EFI_INVALID_PARAMETER;

   }

@@ -172,20 +171,20 @@ ArchSetupExceptionStack (
   //

   // One task gate descriptor and one task-state segment are needed.

   //

-  if (StackSwitchData->X64.ExceptionTssDescSize < sizeof (IA32_TSS_DESCRIPTOR)) {

+  if (StackSwitchData->ExceptionTssDescSize < sizeof (IA32_TSS_DESCRIPTOR)) {

     return EFI_INVALID_PARAMETER;

   }

 

-  if (StackSwitchData->X64.ExceptionTssSize < sizeof (IA32_TASK_STATE_SEGMENT)) {

+  if (StackSwitchData->ExceptionTssSize < sizeof (IA32_TASK_STATE_SEGMENT)) {

     return EFI_INVALID_PARAMETER;

   }

 

   //

   // Interrupt stack table supports only 7 vectors.

   //

-  TssDesc = StackSwitchData->X64.ExceptionTssDesc;

-  Tss     = StackSwitchData->X64.ExceptionTss;

-  if (StackSwitchData->X64.StackSwitchExceptionNumber > ARRAY_SIZE (Tss->IST)) {

+  TssDesc = StackSwitchData->ExceptionTssDesc;

+  Tss     = StackSwitchData->ExceptionTss;

+  if (StackSwitchData->StackSwitchExceptionNumber > ARRAY_SIZE (Tss->IST)) {

     return EFI_INVALID_PARAMETER;

   }

 

@@ -196,19 +195,19 @@ ArchSetupExceptionStack (
   AsmReadGdtr (&Gdtr);

 

   GdtSize = (UINTN)TssDesc + sizeof (IA32_TSS_DESCRIPTOR) -

-            (UINTN)(StackSwitchData->X64.GdtTable);

-  if ((UINTN)StackSwitchData->X64.GdtTable != Gdtr.Base) {

-    CopyMem (StackSwitchData->X64.GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit + 1);

-    Gdtr.Base  = (UINTN)StackSwitchData->X64.GdtTable;

+            (UINTN)(StackSwitchData->GdtTable);

+  if ((UINTN)StackSwitchData->GdtTable != Gdtr.Base) {

+    CopyMem (StackSwitchData->GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit + 1);

+    Gdtr.Base  = (UINTN)StackSwitchData->GdtTable;

     Gdtr.Limit = (UINT16)GdtSize - 1;

   }

 

-  if ((UINTN)StackSwitchData->X64.IdtTable != Idtr.Base) {

-    Idtr.Base = (UINTN)StackSwitchData->X64.IdtTable;

+  if ((UINTN)StackSwitchData->IdtTable != Idtr.Base) {

+    Idtr.Base = (UINTN)StackSwitchData->IdtTable;

   }

 

-  if (StackSwitchData->X64.IdtTableSize > 0) {

-    Idtr.Limit = (UINT16)(StackSwitchData->X64.IdtTableSize - 1);

+  if (StackSwitchData->IdtTableSize > 0) {

+    Idtr.Limit = (UINT16)(StackSwitchData->IdtTableSize - 1);

   }

 

   //

@@ -232,20 +231,20 @@ ArchSetupExceptionStack (
   // Fixup exception task descriptor and task-state segment

   //

   ZeroMem (Tss, sizeof (*Tss));

-  StackTop = StackSwitchData->X64.KnownGoodStackTop - CPU_STACK_ALIGNMENT;

+  StackTop = StackSwitchData->KnownGoodStackTop - CPU_STACK_ALIGNMENT;

   StackTop = (UINTN)ALIGN_POINTER (StackTop, CPU_STACK_ALIGNMENT);

-  IdtTable = StackSwitchData->X64.IdtTable;

-  for (Index = 0; Index < StackSwitchData->X64.StackSwitchExceptionNumber; ++Index) {

+  IdtTable = StackSwitchData->IdtTable;

+  for (Index = 0; Index < StackSwitchData->StackSwitchExceptionNumber; ++Index) {

     //

     // Fixup IST

     //

     Tss->IST[Index] = StackTop;

-    StackTop       -= StackSwitchData->X64.KnownGoodStackSize;

+    StackTop       -= StackSwitchData->KnownGoodStackSize;

 

     //

     // Set the IST field to enable corresponding IST

     //

-    Vector = StackSwitchData->X64.StackSwitchExceptions[Index];

+    Vector = StackSwitchData->StackSwitchExceptions[Index];

     if ((Vector >= CPU_EXCEPTION_NUM) ||

         (Vector >= (Idtr.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR)))

     {

@@ -263,7 +262,7 @@ ArchSetupExceptionStack (
   //

   // Load current task

   //

-  AsmWriteTr ((UINT16)((UINTN)StackSwitchData->X64.ExceptionTssDesc - Gdtr.Base));

+  AsmWriteTr ((UINT16)((UINTN)StackSwitchData->ExceptionTssDesc - Gdtr.Base));

 

   //

   // Publish IDT