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authorGao, Zhichao <zhichao.gao@intel.com>2020-11-12 13:55:51 +0800
committermergify[bot] <37929162+mergify[bot]@users.noreply.github.com>2020-11-17 19:26:50 +0000
commit99e5cf55745345394d25a9fd2abeda1f6c17623e (patch)
treec0c50cf86b80397464993abcdbcc3c6e116c5a94
parentbe7dc487273f50bd6be3f8992d6bdd6c8c38d888 (diff)
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ArmVirtPkg/ArmVirtQemuKernel.dsc: Enable MD5 while enable iSCSI
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3003 There is a plan to make MD5 disable as default. The new MACRO ENABLE_MD5_DEPRECATED_INTERFACES would be introduced to enable MD5. Make the definition ahead of the change to avoid build error after the MACRO changed. Enable iSCSI. Signed-off-by: Zhichao Gao <zhichao.gao@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ard Biesheuvel <ard.biesheuvel@arm.com> Cc: Leif Lindholm <leif@nuviainc.com> Message-Id: <20201112055558.2348-7-zhichao.gao@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
-rw-r--r--ArmVirtPkg/ArmVirtQemuKernel.dsc5
1 files changed, 4 insertions, 1 deletions
diff --git a/ArmVirtPkg/ArmVirtQemuKernel.dsc b/ArmVirtPkg/ArmVirtQemuKernel.dsc
index 9449a01d6e..f447c62f68 100644
--- a/ArmVirtPkg/ArmVirtQemuKernel.dsc
+++ b/ArmVirtPkg/ArmVirtQemuKernel.dsc
@@ -1,7 +1,7 @@
#
# Copyright (c) 2011-2015, ARM Limited. All rights reserved.
# Copyright (c) 2014, Linaro Limited. All rights reserved.
-# Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
+# Copyright (c) 2015 - 2020, Intel Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -38,6 +38,7 @@
DEFINE NETWORK_SNP_ENABLE = FALSE
DEFINE NETWORK_TLS_ENABLE = FALSE
DEFINE NETWORK_ALLOW_HTTP_CONNECTIONS = TRUE
+ DEFINE NETWORK_ISCSI_ENABLE = TRUE
!if $(NETWORK_SNP_ENABLE) == TRUE
!error "NETWORK_SNP_ENABLE is IA32/X64/EBC only"
@@ -84,6 +85,8 @@
UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
[BuildOptions]
+!include NetworkPkg/NetworkBuildOptions.dsc.inc
+
#
# We need to avoid jump tables in SEC modules, so that the PE/COFF
# self-relocation code itself is guaranteed to be position independent.