ArmPkg: Tidy GIC code before changes.

This change is purely cosmetic, to tidy some code before change.
Mods involve:
    Re-order #includes
    Reformat comments.
    Use ns consistently (always "100ns" not sometimes "100 nS")
    Split overlength code lines.
    Make protocol functions STATIC.
    Remove "Horor vacui" comments.
    Rationalize GIC register address calculations
    Replace explicit test and assert with ASSERT_EFI_ERROR.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Girish Pathak <girish.pathak@arm.com>
Signed-off-by: Alexei Fedorov <alexei.fedorov@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

1 files changed, 53 insertions, 29 deletions

diff --git a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c
index 8af97a93b1..50b51ffcf5 100644
--- a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c
+++ b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c
@@ -1,6 +1,6 @@
 /** @file

 *

-*  Copyright (c) 2011-2016, ARM Limited. All rights reserved.

+*  Copyright (c) 2011-2017, ARM Limited. All rights reserved.

 *

 *  This program and the accompanying materials

 *  are licensed and made available under the terms and conditions of the BSD License

@@ -33,6 +33,7 @@ STATIC UINTN mGicRedistributorsBase;
   @retval EFI_DEVICE_ERROR  Hardware could not be programmed.

 

 **/

+STATIC

 EFI_STATUS

 EFIAPI

 GicV3EnableInterruptSource (

@@ -60,6 +61,7 @@ GicV3EnableInterruptSource (
   @retval EFI_DEVICE_ERROR  Hardware could not be programmed.

 

 **/

+STATIC

 EFI_STATUS

 EFIAPI

 GicV3DisableInterruptSource (

@@ -88,6 +90,7 @@ GicV3DisableInterruptSource (
   @retval EFI_DEVICE_ERROR  InterruptState is not valid

 

 **/

+STATIC

 EFI_STATUS

 EFIAPI

 GicV3GetInterruptSourceState (

@@ -101,7 +104,11 @@ GicV3GetInterruptSourceState (
     return EFI_UNSUPPORTED;

   }

 

-  *InterruptState = ArmGicIsInterruptEnabled (mGicDistributorBase, mGicRedistributorsBase, Source);

+  *InterruptState = ArmGicIsInterruptEnabled (

+                      mGicDistributorBase,

+                      mGicRedistributorsBase,

+                      Source

+                      );

 

   return EFI_SUCCESS;

 }

@@ -117,6 +124,7 @@ GicV3GetInterruptSourceState (
   @retval EFI_DEVICE_ERROR  Hardware could not be programmed.

 

 **/

+STATIC

 EFI_STATUS

 EFIAPI

 GicV3EndOfInterrupt (

@@ -137,13 +145,15 @@ GicV3EndOfInterrupt (
   EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs.

 

   @param  InterruptType    Defines the type of interrupt or exception that

-                           occurred on the processor.This parameter is processor architecture specific.

+                           occurred on the processor. This parameter is

+                           processor architecture specific.

   @param  SystemContext    A pointer to the processor context when

                            the interrupt occurred on the processor.

 

   @return None

 

 **/

+STATIC

 VOID

 EFIAPI

 GicV3IrqInterruptHandler (

@@ -168,14 +178,12 @@ GicV3IrqInterruptHandler (
     // Call the registered interrupt handler.

     InterruptHandler (GicInterrupt, SystemContext);

   } else {

-    DEBUG ((EFI_D_ERROR, "Spurious GIC interrupt: 0x%x\n", GicInterrupt));

+    DEBUG ((DEBUG_ERROR, "Spurious GIC interrupt: 0x%x\n", GicInterrupt));

     GicV3EndOfInterrupt (&gHardwareInterruptV3Protocol, GicInterrupt);

   }

 }

 

-//

 // The protocol instance produced by this driver

-//

 EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV3Protocol = {

   RegisterInterruptSource,

   GicV3EnableInterruptSource,

@@ -242,17 +250,16 @@ GicV3DxeInitialize (
   UINT64                  CpuTarget;

   UINT64                  MpId;

 

-  // Make sure the Interrupt Controller Protocol is not already installed in the system.

+  // Make sure the Interrupt Controller Protocol is not already installed in

+  // the system.

   ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);

 

   mGicDistributorBase    = PcdGet64 (PcdGicDistributorBase);

   mGicRedistributorsBase = PcdGet64 (PcdGicRedistributorsBase);

   mGicNumInterrupts      = ArmGicGetMaxNumInterrupts (mGicDistributorBase);

 

-  //

   // We will be driving this GIC in native v3 mode, i.e., with Affinity

   // Routing enabled. So ensure that the ARE bit is set.

-  //

   if (!FeaturePcdGet (PcdArmGicV3WithV2Legacy)) {

     MmioOr32 (mGicDistributorBase + ARM_GIC_ICDDCR, ARM_GIC_ICDDCR_ARE);

   }

@@ -270,51 +277,65 @@ GicV3DxeInitialize (
       );

   }

 

-  //

   // Targets the interrupts to the Primary Cpu

-  //

 

   if (FeaturePcdGet (PcdArmGicV3WithV2Legacy)) {

-    // Only Primary CPU will run this code. We can identify our GIC CPU ID by reading

-    // the GIC Distributor Target register. The 8 first GICD_ITARGETSRn are banked to each

-    // connected CPU. These 8 registers hold the CPU targets fields for interrupts 0-31.

-    // More Info in the GIC Specification about "Interrupt Processor Targets Registers"

-    //

-    // Read the first Interrupt Processor Targets Register (that corresponds to the 4

-    // first SGIs)

+    // Only Primary CPU will run this code. We can identify our GIC CPU ID by

+    // reading the GIC Distributor Target register. The 8 first

+    // GICD_ITARGETSRn are banked to each connected CPU. These 8 registers

+    // hold the CPU targets fields for interrupts 0-31. More Info in the GIC

+    // Specification about "Interrupt Processor Targets Registers"

+

+    // Read the first Interrupt Processor Targets Register (that corresponds

+    // to the 4 first SGIs)

     CpuTarget = MmioRead32 (mGicDistributorBase + ARM_GIC_ICDIPTR);

 

-    // The CPU target is a bit field mapping each CPU to a GIC CPU Interface. This value

-    // is 0 when we run on a uniprocessor platform.

+    // The CPU target is a bit field mapping each CPU to a GIC CPU Interface.

+    // This value is 0 when we run on a uniprocessor platform.

     if (CpuTarget != 0) {

       // The 8 first Interrupt Processor Targets Registers are read-only

       for (Index = 8; Index < (mGicNumInterrupts / 4); Index++) {

-        MmioWrite32 (mGicDistributorBase + ARM_GIC_ICDIPTR + (Index * 4), CpuTarget);

+        MmioWrite32 (

+          mGicDistributorBase + ARM_GIC_ICDIPTR + (Index * 4),

+          CpuTarget

+          );

       }

     }

   } else {

     MpId = ArmReadMpidr ();

-    CpuTarget = MpId & (ARM_CORE_AFF0 | ARM_CORE_AFF1 | ARM_CORE_AFF2 | ARM_CORE_AFF3);

+    CpuTarget = MpId &

+      (ARM_CORE_AFF0 | ARM_CORE_AFF1 | ARM_CORE_AFF2 | ARM_CORE_AFF3);

+

+    if ((MmioRead32 (

+           mGicDistributorBase + ARM_GIC_ICDDCR

+         ) & ARM_GIC_ICDDCR_DS) != 0) {

 

-    if ((MmioRead32 (mGicDistributorBase + ARM_GIC_ICDDCR) & ARM_GIC_ICDDCR_DS) != 0) {

-      //

       // If the Disable Security (DS) control bit is set, we are dealing with a

       // GIC that has only one security state. In this case, let's assume we are

       // executing in non-secure state (which is appropriate for DXE modules)

       // and that no other firmware has performed any configuration on the GIC.

       // This means we need to reconfigure all interrupts to non-secure Group 1

       // first.

-      //

-      MmioWrite32 (mGicRedistributorsBase + ARM_GICR_CTLR_FRAME_SIZE + ARM_GIC_ICDISR, 0xffffffff);

+

+      MmioWrite32 (

+        mGicRedistributorsBase + ARM_GICR_CTLR_FRAME_SIZE + ARM_GIC_ICDISR,

+        0xffffffff

+        );

 

       for (Index = 32; Index < mGicNumInterrupts; Index += 32) {

-        MmioWrite32 (mGicDistributorBase + ARM_GIC_ICDISR + Index / 8, 0xffffffff);

+        MmioWrite32 (

+          mGicDistributorBase + ARM_GIC_ICDISR + Index / 8,

+          0xffffffff

+          );

       }

     }

 

     // Route the SPIs to the primary CPU. SPIs start at the INTID 32

     for (Index = 0; Index < (mGicNumInterrupts - 32); Index++) {

-      MmioWrite32 (mGicDistributorBase + ARM_GICD_IROUTER + (Index * 8), CpuTarget | ARM_GICD_IROUTER_IRM);

+      MmioWrite32 (

+        mGicDistributorBase + ARM_GICD_IROUTER + (Index * 8),

+        CpuTarget | ARM_GICD_IROUTER_IRM

+        );

     }

   }

 

@@ -331,7 +352,10 @@ GicV3DxeInitialize (
   ArmGicEnableDistributor (mGicDistributorBase);

 

   Status = InstallAndRegisterInterruptService (

-          &gHardwareInterruptV3Protocol, GicV3IrqInterruptHandler, GicV3ExitBootServicesEvent);

+             &gHardwareInterruptV3Protocol,

+             GicV3IrqInterruptHandler,

+             GicV3ExitBootServicesEvent

+             );

 

   return Status;

 }